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公开(公告)号：US20070266374A1
公开(公告)日：2007-11-15
申请号：US11431926
申请日：2006-05-11
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F9/3861 , G06F9/462
摘要： A data processor 2 has privilege levels associated with it including a user level and a privileged level. The processor 2 also has multiple stack memories which can be used including one or more process stacks, a main stack and a deep stack. The stack memory to be used is de-coupled from the privilege level. An activation level state variable tracking the number of pending exceptions is held by the processor and used to modify which stack memory stores pending state values when an exception occurs. If the system is at a base level of activation, corresponding to currently no pending exceptions, then when an exception occurs the current state data is saved on the process stack with the main stack being available for the exception handling code. Particular exceptions can be flagged as requiring use of a deep stack rather than either the process stack or the main stack. If the system is not at the base level of activation, then the main stack is used to save state variables when an exception occurs rather than the process stack.
摘要翻译： 数据处理器2具有与其相关联的特权级别，其包括用户级别和特权级别。 处理器2还具有可以使用的多个堆栈存储器，包括一个或多个处理堆栈，主堆栈和深堆栈。 要使用的堆栈内存从特权级别去耦合。 跟踪待处理异常的数量的激活级状态变量由处理器保存，并用于修改哪个堆栈存储器在发生异常时存储待处理的状态值。 如果系统处于激活的基本级别，对应于当前没有挂起的异常，则当发生异常时，当前状态数据保存在进程堆栈中，主堆栈可用于异常处理代码。 可以将特殊异常标记为需要使用深栈，而不是使用进程堆栈或主堆栈。 如果系统不在激活的基本级别，则主堆栈用于在异常发生时保存状态变量而不是进程堆栈。
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2.发明申请Alias management within a virtually indexed and physically tagged cache memory 有权虚拟索引和物理标记的高速缓存内存中的别名管理公开(公告)号：US20070033318A1
公开(公告)日：2007-02-08
申请号：US11197523
申请日：2005-08-05
CPC分类号： G06F12/1045 , G06F12/0864 , G06F12/1063
摘要： A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.
摘要翻译： 描述了虚拟索引和物理标记的存储器，其具有可以超过最小页表大小的高速缓存路径大小，使得高速缓存路径12内的别名虚拟地址VA可以映射到相同的物理地址PA。 混叠管理逻辑10允许来自相同物理地址的数据的多个副本被存储在给定或不同的高速缓存方式内的高速缓存内的不同虚拟索引处。
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公开(公告)号：US20050210328A1
公开(公告)日：2005-09-22
申请号：US10801136
申请日：2004-03-16
IPC分类号： G06F11/00 , G06F11/07 , G06F11/273
CPC分类号： G06F11/2733 , G06F11/079
摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
摘要翻译： 描述了具有中央处理单元4和诊断机构10的数据处理系统2。 中央处理单元4可切换到掉电模式，从而可以恢复正常操作模式。 当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。 通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。 程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。
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公开(公告)号：US5978908A
公开(公告)日：1999-11-02
申请号：US735864
申请日：1996-10-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： A computer instruction supply system has store and fetch circuitry for obtaining a sequence of instructions, test circuitry for locating the first instruction in the sequence to be enabled, and for testing separately successive instructions in the sequence to locate any branch instruction which is predicted to be taken and control circuitry to disregard target addresses of branch instructions in the sequence prior to the first instruction to be executed.
摘要翻译： 计算机指令提供系统具有用于获得指令序列的存储和获取电路，用于定位要启用的序列中的第一指令的测试电路，以及用于在该序列中单独测试连续的指令以定位预测为 拍摄和控制电路在第一指令执行之前忽略该序列中的分支指令的目标地址。
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公开(公告)号：US5867698A
公开(公告)日：1999-02-02
申请号：US735785
申请日：1996-10-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： A branch target buffer comprises a partitioned cache memory having for each partition a CAM array holding the least significant bits of a fetch address, a RAM holding the least significant bits of a target address, and comparators for comparing the most significant bits of the fetch and target addresses to control entry of a branch instruction into the buffer.
摘要翻译： 分支目标缓冲器包括分区高速缓存存储器，其对于每个分区具有保持取指地址的最低有效位的CAM阵列，保存目标地址的最低有效位的RAM，以及用于比较提取的最高有效位和 目标地址，以控制分支指令进入缓冲区。
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6.发明申请公开(公告)号：US20070170269A1
公开(公告)日：2007-07-26
申请号：US11649370
申请日：2007-01-04
IPC分类号： G06K19/06
CPC分类号： G06F13/4265
摘要： Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not communicating triggers modified behaviour. This can provide that the predetermined transaction protocol is not broken and/or complete a partially completed transaction when the domain concerned has recovered from an error or other event which disrupted the communication.
摘要翻译： 在集成电路2内，可独立控制的域4,6,8,10,12,14可能无法完成域之间发生的待处理事务。 每个域被提供有状态机20,22，该状态机响应于另一个域内的状态机的状态，并且当这指示另一个域不通信触发修改的行为时。 这可以规定，当有关的域已经从错误或其他中断通信的事件中恢复时，预定的事务协议不被破坏和/或完成部分完成的事务。
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公开(公告)号：US20070005938A1
公开(公告)日：2007-01-04
申请号：US11170083
申请日：2005-06-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A data processing apparatus, comprising: a processor for executing instructions; a prefetch unit for prefetching instructions from a memory prior to sending those instructions to said processor for execution; branch prediction logic; and a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information including, identification of an instruction specifying a branch operation, a target address for said branch operation and a prediction as to whether said branch is taken or not; wherein said prefetch unit is operable prior to fetching an instruction from said memory, to access said branch target cache and to determine if there is predetermined information corresponding to said instruction stored within said branch target cache and if there is to retrieve said predetermined information; said branch prediction logic being operable in response to said retrieved predetermined information to predict whether said instruction specifies a branch operation that will be taken and will cause a change in instruction flow, and if so to indicate to said prefetch unit a target address within said memory from which a following instruction should be fetched; wherein said access to said branch target cache is initiated at least one clock cycle before initiating fetching of said instruction from said memory.
摘要翻译： 一种数据处理装置，包括：处理器，用于执行指令; 预取单元，用于在将所述指令发送到所述处理器以执行之前从存储器预取指令; 分支预测逻辑; 以及分支目标缓存，用于存储关于由所述处理器执行的分支操作的预定信息，所述预定信息包括指定分支操作的指令的识别，所述分支操作的目标地址以及关于所述分支是否被采取的预测 ; 其中所述预取单元在从所述存储器获取指令之前可操作，以访问所述分支目标高速缓存并且确定是否存在对应于存储在所述分支目标高速缓存内的所述指令的预定信息，以及是否检索所述预定信息; 所述分支预测逻辑可响应于所述检索的预定信息进行操作，以预测所述指令是否指定将被采用的分支操作，并且将导致指令流程的改变，并且如果是，则向所述预取单元指示所述存储器内的目标地址 应从中获取以下指令; 其中所述对所述分支目标高速缓存的访问在开始从所述存储器获取所述指令之前至少一个时钟周期被启动。
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8.发明申请Condition branch instruction encoding within a multiple instruction set data processing system 有权在多指令集数据处理系统中进行条件分支指令编码公开(公告)号：US20060224861A1
公开(公告)日：2006-10-05
申请号：US11095655
申请日：2005-04-01
IPC分类号： G06F9/40
CPC分类号： G06F9/3806 , G06F9/30072 , G06F9/30149 , G06F9/30189 , G06F9/30196 , G06F9/3844
摘要： A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the two different instruction sets are arranged to use the same instruction encoding.
摘要翻译： 数据处理系统可在第一状态下操作，以使用具有第一指令集编码的第一指令集。 数据处理系统还可在第二状态下操作以使用具有第二指令编码的第二指令集。 在两个不同的指令集中提供的条件转移指令被设置为使用相同的指令编码。
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公开(公告)号：US20050246585A1
公开(公告)日：2005-11-03
申请号：US11085263
申请日：2005-03-22
IPC分类号： G06F11/00 , G06F11/07 , G06F11/273
CPC分类号： G06F11/079 , G06F11/2733
摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
摘要翻译： 描述了具有中央处理单元4和诊断机构10的数据处理系统2.中央处理单元4可切换到能够恢复到正常操作模式的掉电模式。 当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。 通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。 程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。
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公开(公告)号：US5873115A
公开(公告)日：1999-02-16
申请号：US735863
申请日：1996-10-23
CPC分类号： G06F9/3806
摘要： A cache memory has a plurality of cache partitions each having a CAM array, a data RAM and output control circuitry which determines a different priority for each cache partition and permits a cache hit output only from one partition which has the highest priority with a cache hit.
摘要翻译： 高速缓存存储器具有多个高速缓存分区，每个高速缓存分区具有CAM阵列，数据RAM和输出控制电路，其确定每个高速缓存分区的不同优先级，并允许仅从具有最高优先级的一个分区的高速缓存命中输出与高速缓存命中 。
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