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公开(公告)号：US07035318B2
公开(公告)日：2006-04-25
申请号：US10105191
申请日：2002-03-26
CPC分类号： H04B1/7115 , H04B1/712
摘要： A receiving unit for receiving a CDMA system signal having a plurality of multipath components is intended to reduce the size. A receiving section receives a CDMA system signal. A storage section stores the signal received by the receiving section. A demodulation section demodulates each of multipath components included in the received signal stored in the storage section with a despreading code. A control section controls for demodulating a plurality of the multipath components by causing the demodulation section to perform a time division multiplex process. A Rake combining section performs the maximal ratio combining of output from the demodulation section to generate a demodulated signal.
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公开(公告)号：US06678315B1
公开(公告)日：2004-01-13
申请号：US09447234
申请日：1999-11-23
IPC分类号： H04L516
CPC分类号： H04J13/10 , H03K3/84 , H04J13/0022
摘要： A code phase setting method in a PN coder which includes a shift register is provided. According to the method, an initial value is set in the shift register and a direction is selected among two directions in which direction a value in the shift register is shifted. Then, a code phase is set by shifting the initial value in the direction a necessary number of times.
摘要翻译： 提供了包括移位寄存器的PN编码器中的码相位设定方法。 根据该方法，在移位寄存器中设置初始值，并且在移位寄存器中的值偏移方向的两个方向上选择方向。 然后，通过将初始值沿着必要次数的方向移位来设置码相位。
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公开(公告)号：US07032161B2
公开(公告)日：2006-04-18
申请号：US10223216
申请日：2002-08-20
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/09 , H03M13/23 , H03M13/39 , H03M13/41
摘要： An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.
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公开(公告)号：US06493844B1
公开(公告)日：2002-12-10
申请号：US09311722
申请日：1999-05-14
IPC分类号： H03M1300
CPC分类号： H03M13/091 , H03M13/09 , H03M13/23 , H03M13/39 , H03M13/41
摘要： An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string generated at the transmitter so that errors in the reception bit string are detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.
摘要翻译： 接收机的误差检测器包括反馈移位寄存器。 反馈移位寄存器中的移位方向与通过使用指定的生成多项式生成传输位串时的发送器处的移位方向相反。 接收比特串以相反的顺序被输入到反馈移位寄存器，以便在发送器处产生的发送比特串，从而通过获得余数来检测接收比特串中的错误。 接收机处的另一个误差检测器包括第一和第二反馈移位寄存器。 第一和第二反馈移位寄存器中的相应移位方向与发送器在生成传输位串时的移位方向相同且相反。 接收比特串以与生成发送比特串相同的顺序输入到第一反馈移位寄存器，而接收比特串以相反的顺序被输入到第二反馈移位寄存器，以产生发送比特串 。 通过比较由第一和第二反馈移位寄存器获得的各个余数来检测接收位串中的错误。 这减少了错误检测所需的处理时间，并提高了检测传输数据中错误的效率。
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公开(公告)号：US20060150067A1
公开(公告)日：2006-07-06
申请号：US11350858
申请日：2006-02-10
IPC分类号： H03M13/03
CPC分类号： H03M13/091 , H03M13/09 , H03M13/23 , H03M13/39 , H03M13/41
摘要： An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.
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6.发明授权Adder circuit, integrating circuit which uses the adder circuit, and synchronism detection circuit which uses the integrating circuit 有权加法器电路，使用加法器电路的积分电路和使用积分电路的同步检测电路公开(公告)号：US06647405B1
公开(公告)日：2003-11-11
申请号：US09522404
申请日：2000-03-09
IPC分类号： G06F750
CPC分类号： G06F7/5052
摘要： An adding circuit which receives addend data and augend data, each of which consists of a plurality of bits, and sums the addend and augend data, comprises: a plurality of addition blocks, each of which is used to add a predetermined number of bits of the addend data to a like number of bits of the augend data, and for outputting both the result obtained by adding the predetermined number of bits and a carry-out signal, wherein, when a carry-out occurs for one of the addition blocks, in accordance with a carry-out signal from a lower rank and a set comprising the addend data and the augend data, the pertinent addition block responds to the pertinent carry-out, and wherein, when a carry-out does not occur for the addition block in accordance with the set comprising the addend data and the augend data, the pertinent addition block responds to the carry-out and generates a block addition end signal which indicates that the addition performed by the addition block has been completed.
摘要翻译： 一种附加电路，其接收加数据和加数数据，每个数据包括多个比特，并且加法和加数数据相加，包括：多个加法块，每个加法块用于将预定数量的比特 将加数数据加到类似数量的加法数据位，并输出通过相加预定位数和执行输出信号而获得的结果，其中当对于一个加法块发生进位输出时， 根据来自下级的进位信号和包括加法数据和加数数据的集合，相关的加法块响应相关的进位输出，并且其中当不进行加法运算时 根据包括加数数据和加数数据的集合，相关附加块响应进位输出，并产生指示由加法块执行的相加已经完成的块加法结束信号。
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公开(公告)号：US07051059B2
公开(公告)日：2006-05-23
申请号：US09818350
申请日：2001-03-27
IPC分类号： G06F17/17
CPC分类号： H03H17/0219 , H03H17/0294 , H03H17/0621
摘要： When changing the number of oversamples is performed, tap factors selected by selectors, which respectively correspond to holding parts in a shift register, are changed back to a predetermined number of tap factors used before the changing of the number of oversamples, in which every time input data is accepted, the changes of the tap factors are performed in sequence, starting from the selector corresponding to the holding part at the input side. This allows the individual selectors to select proper tap factors according to the input data after the changing of the number of oversamples. As a result, the continuity of the output data is maintained even before and after the number of oversamples is changed.
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8.发明授权公开(公告)号：US07233613B2
公开(公告)日：2007-06-19
申请号：US09789863
申请日：2001-02-21
IPC分类号： H04B1/00
CPC分类号： H04B1/708
摘要： The present invention provides a synchronization establishing device and method for establishing synchronization at a high speed in a receiver. This synchronization establishing device includes a storage unit that accumulates reception data, and a matched filter that reads out the reception data accumulated in the storage unit in parallel and determines a correlation value by obtaining correlation between a common code and the reception data in parallel.
摘要翻译： 本发明提供了一种用于在接收机中高速建立同步的同步建立装置和方法。 该同步建立装置包括累积接收数据的存储单元和并行地读出存储单元中累积的接收数据的并行确定相关值的匹配滤波器，并且通过并行地获得公共码与接收数据之间的相关性来确定相关值。
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9.发明授权Cell search method, communication synchronization apparatus, portable terminal apparatus, and recording medium 失效小区搜索方法，通信同步装置，便携式终端装置和记录介质公开(公告)号：US07085252B1
公开(公告)日：2006-08-01
申请号：US09540878
申请日：2000-03-31
IPC分类号： H04B7/216
CPC分类号： H04W48/16 , H04B1/7075 , H04B1/70755 , H04B1/7083 , H04B1/709 , H04B2201/70702
摘要： A power threshold value (12) is set to be compared with a correlation power value detected by a correlator (2) and a power conversion section (4). As a result of comparison by a comparator (13), only the correlation power values that exceed the threshold value (12) are stored in a power value memory (14), and unnecessary correlation values at noise levels are not stored in the memory (14) so that the number of power values stored can be decreased. With this construction, the necessary memory capacity can be decreased, and the process of searching for the maximum value from the correlation power values stored in the memory (14) can be performed at a higher speed.
摘要翻译： 功率阈值（12）被设置为与相关器（2）和功率转换部分（4）检测的相关功率值进行比较。 作为比较器（13）进行比较的结果，只有超过阈值（12）的相关功率值被存储在功率值存储器（14）中，噪声水平的不必要的相关值不被存储在存储器 14），使得可以减少存储的功率值的数量。 利用这种结构，可以减少必要的存储容量，并且可以以更高的速度执行从存储器（14）中存储的相关功率值搜索最大值的处理。
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10.发明授权FIR filter, method of operating the same, semiconductor integrated circuit including FIR filter, and communication system for transmitting data filtered by FIR filter 失效FIR滤波器，其操作方法，包括FIR滤波器的半导体集成电路和用于发送由FIR滤波器滤波的数据的通信系统公开(公告)号：US07028062B2
公开(公告)日：2006-04-11
申请号：US09928803
申请日：2001-08-13
IPC分类号： G06F17/10
CPC分类号： H03H17/06 , G06F9/3893
摘要： The FIR filter separately receives input data consisting of transmitting information and composed of bit strings, and additional data which is added in order to transmit the input data. The input data is operated with the additional data. A difference between the additional data corresponding to previous data (for instance, most recent data) among the input data and the additional data corresponding present data is obtained, and the difference and the previous data are operated. Then, the operation results are added and the resultant is outputted as a filter response. The input data and the additional data are separately received to be operated so that the circuit scale of the filter is reduced. Therefore, a chip of the semiconductor integrated circuit can be downsized and thereby cost reduction in the communication system can be realized.
摘要翻译： FIR滤波器分别接收由发送信息组成的输入数据和由比特串组成的附加数据，以便传送输入数据。 输入数据使用附加数据进行操作。 获得与输入数据中的先前数据（例如最新数据）相对应的附加数据与对应的当前数据的附加数据之间的差异，并且操作差值和先前数据。 然后，将运算结果相加，作为滤波器响应输出。 输入数据和附加数据被单独接收以被操作，使得滤波器的电路规模减小。 因此，可以使半导体集成电路的芯片小型化，从而能够实现通信系统的成本降低。
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