Customizable memory indexing functions
    1.
    发明申请
    Customizable memory indexing functions 有权
    可定制的内存索引功能

    公开(公告)号:US20080256328A1

    公开(公告)日:2008-10-16

    申请号:US11786581

    申请日:2007-04-12

    IPC分类号: G06F9/34

    CPC分类号: G06F12/0864

    摘要: Methods and apparatus related to memory indexing. Receiving indications of an indexing function for use with a memory. Performing indexing functions with a processor before addressing a memory location. Referencing a customizable lookup table to determine a memory location. Translating a computer program to control a computer system to use a desired indexing function. Determining desired indexing functions based on performance of a computer system.

    摘要翻译: 与记忆索引相关的方法和设备。 接收与存储器一起使用的索引功能的指示。 在寻址内存位置之前,使用处理器执行索引功能。 引用可定制的查找表来确定内存位置。 翻译计算机程序以控制计算机系统使用所需的索引功能。 根据计算机系统的性能确定所需的索引功能。

    Customizable memory indexing functions
    2.
    发明授权
    Customizable memory indexing functions 有权
    可定制的内存索引功能

    公开(公告)号:US07856529B2

    公开(公告)日:2010-12-21

    申请号:US11786581

    申请日:2007-04-12

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0864

    摘要: Methods and apparatus related to memory indexing. Receiving indications of an indexing function for use with a memory. Performing indexing functions with a processor before addressing a memory location. Referencing a customizable lookup table to determine a memory location. Translating a computer program to control a computer system to use a desired indexing function. Determining desired indexing functions based on performance of a computer system.

    摘要翻译: 与记忆索引相关的方法和设备。 接收与存储器一起使用的索引功能的指示。 在寻址内存位置之前,使用处理器执行索引功能。 引用可定制的查找表来确定内存位置。 翻译计算机程序以控制计算机系统使用所需的索引功能。 根据计算机系统的性能确定所需的索引功能。

    BEST CLOCK FREQUENCY SEARCH FOR FPGA-BASED DESIGN
    3.
    发明申请
    BEST CLOCK FREQUENCY SEARCH FOR FPGA-BASED DESIGN 失效
    基于FPGA的设计的最佳时钟频率搜索

    公开(公告)号:US20130268907A1

    公开(公告)日:2013-10-10

    申请号:US13441053

    申请日:2012-04-06

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5031

    摘要: Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints.

    摘要翻译: 搜索用于基于集成电路的设计的期望时钟频率可以接收基于指定硬件设计的代码执行的硬件合成作业的定时结果。 可以在不修改代码的情况下自动生成指定与在硬件合成作业中使用的不同的一个或多个不同的时钟频率的一个或多个不同的时序约束。 可以自动产生用相应的一个或多个不同时序约束运行的硬件合成作业的一个或多个实例。 基于硬件合成作业的一个或多个实例是否符合其相应的定时,自动生成和产卵可以重复直到满足终止标准,和/或从不同的时序约束识别硬件设计的期望的成功时序约束 约束。

    INCENTIVIZING CONTENT-RECEIVERS IN SOCIAL NETWORKS
    4.
    发明申请
    INCENTIVIZING CONTENT-RECEIVERS IN SOCIAL NETWORKS 审中-公开
    激励社会网络内容接收者

    公开(公告)号:US20120041850A1

    公开(公告)日:2012-02-16

    申请号:US12853981

    申请日:2010-08-10

    申请人: Rodric Rabbah

    发明人: Rodric Rabbah

    IPC分类号: G06Q30/00 G06Q10/00

    CPC分类号: G06Q50/01 G06Q30/02 G06Q40/12

    摘要: An embodiment of the invention provides a method including receiving a request to publish first content on a system from a user. A fee is imposed to the user to publish the first content. The first content is published on the system. In at least one embodiment, an amount of net credits of the user is published on a profile of the user. A credit is provided to the user for each instance the user receives second content from the system, the credit being non-redeemable for cash. The credit is provided to the user at pre-determined time intervals and/or when pre-determined milestones reached. In at least one embodiment, the fee is credited to the user if the first content is a comment to existing content.

    摘要翻译: 本发明的实施例提供了一种方法,包括从用户接收在系统上发布第一内容的请求。 向用户收取费用以发布第一内容。 第一个内容在系统上发布。 在至少一个实施例中,用户的简档上公布了用户的净信用量。 对于用户从系统接收第二内容的每个实例,向用户提供信用,信用是不可兑换的现金。 以预定的时间间隔和/或达到预定的里程碑为用户提供信用。 在至少一个实施例中,如果第一内容是对现有内容的评论,则该费用记入用户。

    Technique for compiling and running high-level programs on heterogeneous computers
    5.
    发明授权
    Technique for compiling and running high-level programs on heterogeneous computers 有权
    在异构计算机上编译和运行高级程序的技术

    公开(公告)号:US08938725B2

    公开(公告)日:2015-01-20

    申请号:US13618523

    申请日:2012-09-14

    IPC分类号: G06F9/44 G06F9/45

    CPC分类号: G06F8/456

    摘要: A technique for compiling and running high-level program on heterogeneous computers may include partitioning a program code into two or more logical units, and compiling each of the logical units into one or more executable entities. At least some of the logical units are compiled into two or more executable entities, the two or more executable entities being different compilations of the same logical unit. The two or more executable entities are compatible to run on respective two or more platforms that have different architecture.

    摘要翻译: 用于在异构计算机上编译和运行高级程序的技术可以包括将程序代码划分为两个或多个逻辑单元,以及将每个逻辑单元编译成一个或多个可执行实体。 至少一些逻辑单元被编译成两个或多个可执行实体,两个或多个可执行实体是同一逻辑单元的不同编译。 两个或多个可执行实体兼容以在具有不同体系结构的相应的两个或多个平台上运行。

    Extraction of functional semantics and isolated dataflow from imperative object oriented languages
    6.
    发明授权
    Extraction of functional semantics and isolated dataflow from imperative object oriented languages 有权
    从强制性面向对象语言中提取功能语义和孤立数据流

    公开(公告)号:US09424010B2

    公开(公告)日:2016-08-23

    申请号:US12870980

    申请日:2010-08-30

    IPC分类号: G06F9/44 G06F9/45

    摘要: Extraction of functional semantics and isolated dataflow from imperative object oriented languages, in one aspect, may include identifying one or more methods and/or classes associated with one or more of a plurality of property labels in a computer code written in object oriented language to extract functional and isolation characteristics in the computer code. The plurality of property labels supported by one or more checking rules, are used to verify that the one or more methods and/or classes identified with the plurality of property labels have isolation characteristics. An object oriented language compiler is provided for supplying the plurality of property labels and checking rules. The object oriented language compiler further may include capability to transform methods into compute tasks and connect the compute tasks so as to create a dataflow graph.

    摘要翻译: 在一方面,从命令性面向对象语言中提取功能语义和隔离数据流可以包括识别与以面向对象语言编写的计算机代码中的多个属性标签中的一个或多个属性标签相关联的一个或多个方法和/或类,以提取 功能和隔离特性在计算机代码中。 由一个或多个检查规则支持的多个属性标签用于验证用多个属性标签标识的一个或多个方法和/或类具有隔离特性。 提供面向对象的语言编译器用于提供多个属性标签和检查规则。 面向对象的语言编译器还可以包括将方法转换成计算任务并连接计算任务以便创建数据流图的能力。

    Technique for compiling and running high-level programs on heterogeneous computers
    8.
    发明授权
    Technique for compiling and running high-level programs on heterogeneous computers 有权
    在异构计算机上编译和运行高级程序的技术

    公开(公告)号:US08789026B2

    公开(公告)日:2014-07-22

    申请号:US13196300

    申请日:2011-08-02

    IPC分类号: G06F9/44 G06F9/45

    CPC分类号: G06F8/456

    摘要: A technique for compiling and running high-level program on heterogeneous computers may include partitioning a program code into two or more logical units, and compiling each of the logical units into one or more executable entities. At least some of the logical units are compiled into two or more executable entities, the two or more executable entities being different compilations of the same logical unit. The two or more executable entities are compatible to run on respective two or more platforms that have different architecture.

    摘要翻译: 用于在异构计算机上编译和运行高级程序的技术可以包括将程序代码划分为两个或多个逻辑单元,以及将每个逻辑单元编译成一个或多个可执行实体。 至少一些逻辑单元被编译成两个或多个可执行实体,两个或多个可执行实体是同一逻辑单元的不同编译。 两个或多个可执行实体兼容以在具有不同体系结构的相应的两个或多个平台上运行。

    Best clock frequency search for FPGA-based design
    9.
    发明授权
    Best clock frequency search for FPGA-based design 失效
    最佳时钟频率搜索基于FPGA的设计

    公开(公告)号:US08566768B1

    公开(公告)日:2013-10-22

    申请号:US13441053

    申请日:2012-04-06

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5031

    摘要: Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints.

    摘要翻译: 搜索用于基于集成电路的设计的期望时钟频率可以接收基于指定硬件设计的代码执行的硬件合成作业的定时结果。 可以在不修改代码的情况下自动生成指定与在硬件合成作业中使用的不同的一个或多个不同的时钟频率的一个或多个不同的时序约束。 可以自动产生用相应的一个或多个不同时序约束运行的硬件合成作业的一个或多个实例。 基于硬件合成作业的一个或多个实例是否符合其相应的定时,自动生成和产卵可以重复,直到满足终止标准,和/或从不同的时序约束识别硬件设计的期望的成功时序约束 约束。