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公开(公告)号：US20210157594A1
公开(公告)日：2021-05-27
申请号：US17103036
申请日：2020-11-24
摘要： A data temporary storage apparatus includes a moving unit coupled to a first storage unit and multiple second storage units. The moving unit receives a moving instruction having contents including a read address, a destination address and a predetermined moving rule. The moving unit further executes the moving instruction to fetch input data by row from the first storage unit according to the read address, and to temporarily stores one after another in an alternate and sequential manner the data in each row to each of the second storage units indicated by the destination address. The data moving, data reading and convolution approaches of the present invention implement in parallel data moving and a convolution operation, achieving a ping-pong operation of convolution units and enhancing convolution efficiency, while reducing memory costs since configuring two data storage spaces in a memory is not necessary.
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公开(公告)号：US20220075522A1
公开(公告)日：2022-03-10
申请号：US17231133
申请日：2021-04-15
IPC分类号： G06F3/06
摘要： A virtual memory management method applied to an intelligent processor including an operation accelerator includes: determining m storage units from a physical memory, the m storage units forming a virtual memory; dividing the m storage units into n storage groups; determining an address mapping relationship for each storage group to obtain n address mapping relationships, the n address mapping relationship being correspondence of between n virtual addresses of the virtual memory and physical addresses of the m storage units, where m and n are dynamically updated according to requirements of the operation accelerator. In the method, the number of the storage units in each storage group can be configured according to requirements of the operation accelerator, and a data storage bit width and a data storage depth of the virtual memory are dynamically updated to thereby improve data access efficiency.
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3.发明申请公开(公告)号：US20220036167A1
公开(公告)日：2022-02-03
申请号：US17335569
申请日：2021-06-01
摘要： An operation method in a convolutional neural network applied to an electronic apparatus having a memory storing convolutional kernel data having undergone a sorting process. The operation method includes: performing the sorting process on a first feature vector of feature map data under process according to a marking sequence corresponding to a first weighting vector of the convolutional kernel data having undergone the sorting process; removing a part of feature values in the first feature vector having undergone the sorting process to generate a second feature vector; and performing a multiply accumulation operation on the basis of the first weighting vector and the second feature vector. The convolutional kernel data having undergone the sorting process is obtained by means of performing sorting and zero-weighting removal processes, and the marking sequence is generated according to the sorting and zero-weighting removal processes corresponding to the first weighting vector.
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公开(公告)号：US20220083857A1
公开(公告)日：2022-03-17
申请号：US17401358
申请日：2021-08-13
摘要： A convolutional neural network operation device includes a scheduling mode unit, a first data processing circuit, a second data processing circuit and a multiple-accumulate (MAC) operation array. The scheduling mode unit determines, according to a quantity and size information of the target convolutional kernels, a target scheduling mode corresponding to a size of a convolutional computing block. The first data processing circuit recombines weight data in the target convolutional kernels and the second data processing circuit recombines input data in a target convolutional layer according to the target scheduling mode. The MAC operation array includes multiple MAC operation cells, and performs a MAC operation based on the recombined weight data and the recombined input data, wherein a quantity of the MAC operation cells used by the MAC operation array in each round of operation corresponds to the size of the convolutional computing block.
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公开(公告)号：US20220092151A1
公开(公告)日：2022-03-24
申请号：US17328006
申请日：2021-05-24
发明人： Fabo BAO , Donghao LIU , Wei ZHU , Chengwei ZHENG
摘要： A convolution calculation apparatus applied for convolution calculation of a convolution layer includes a decompression circuit, a data combination circuit and a calculation circuit. The decompression circuit decompresses compressed weighting data of a convolution kernel of the convolution layer to generate decompressed weighting data. The data combination circuit combines the decompressed weighting data and non-compressed data of the convolution kernel to restore a data order of weighting data of the convolution kernel. The calculation circuit performs calculation according to the weighting data of the convolution kernel and input data of the convolution layer. Since the compressed weighting data of the convolution kernel is transmitted to the convolution calculation apparatus in advance, the compressed weighting data is first decompressed and then convolution calculation is performed accordingly, hence reducing the storage amount and transmission bandwidth used by the convolution kernel in an electronic apparatus.
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公开(公告)号：US20220091780A1
公开(公告)日：2022-03-24
申请号：US17393444
申请日：2021-08-04
发明人： Jianzhi WANG , Wei ZHU , Bingjie HE , Bo LIN , Mingyong SUN
IPC分类号： G06F3/06
摘要： The disclosure provides an intelligent processing apparatus including a processor and a direct memory access (DMA) controller. The processor generates a read command to read data from a memory. An address generation circuit generates multiple first address signals to the memory. A data processing circuit receives data that the memory outputs in response to the multiple first address signals, and performs a data interception process on the data received from the memory according to the read command and a first configuration parameter. A data port transmits the data processed by the data processing circuit to the processor. The multiple first address signals include multiple non-consecutive address signals such that the data read from the memory and processed by the data processing circuit corresponds to n-dimensional data blocks, where n is a positive integer greater than 1.
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公开(公告)号：US20210349692A1
公开(公告)日：2021-11-11
申请号：US17146946
申请日：2021-01-12
摘要： A multiplier includes a multiplier preprocessing circuit, an encoding code, an addition circuit and a partial product selection circuit. The multiplier preprocessing circuit generates different input coding values from a received multiplier according to different operation bit widths. The encoding circuit generates different coded values according to different input coding values, and performs an operation according to different coded values and a received multiplicand to obtain a first partial product. The addition circuit accumulates the first partial product for a corresponding number of times according to different operation bit widths to generate different second partial products. The multiplier supports multiplication of multiple mixed bit widths, and a multiplier unit can be repeatedly used for multiplication operations in encounters with different precisions.
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