公开(公告)号：US20210184664A1

公开(公告)日：2021-06-17

申请号：US16717816

申请日：2019-12-17

Applicant: Silicon Laboratories Inc.

Inventor： Daniel Weyer ,  Raghunandan K. Ranganathan

IPC: H03K5/1534 ,  G04F10/00

Abstract: A method determines a pin-to-pin delay between clock signals having integrally related frequencies. The method includes generating a delay code corresponding to a delay between a first signal edge of a first clock signal received by a first node of an integrated circuit and a second signal edge of a second clock signal received by a second node of the integrated circuit. The delay code is based on a first time code corresponding to the first signal edge, a second time code corresponding to the second signal edge, a first skew code, a second skew code, and a period of the first clock signal or the second clock signal. The first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is integrally related to the first frequency.