公开(公告)号：US20210176020A1

公开(公告)日：2021-06-10

申请号：US16707401

申请日：2019-12-09

Applicant: Silicon Laboratories Inc.

Inventor： Raghunandan K. Ranganathan ,  Kannanthodath V. Jayakumar ,  Srisai R. Seethamraju

IPC: H04L1/20 ,  G01R31/30 ,  G01R31/317 ,  G01R29/26

Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

公开(公告)号：US11228403B2

公开(公告)日：2022-01-18

申请号：US16707401

申请日：2019-12-09

Applicant: Silicon Laboratories Inc.

Inventor： Raghunandan K. Ranganathan ,  Kannanthodath V. Jayakumar ,  Srisai R. Seethamraju

IPC: H04L1/20 ,  G01R31/30 ,  G01R29/26 ,  G01R31/317

Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

公开(公告)号：US20210184664A1

公开(公告)日：2021-06-17

申请号：US16717816

申请日：2019-12-17

Applicant: Silicon Laboratories Inc.

Inventor： Daniel Weyer ,  Raghunandan K. Ranganathan

IPC: H03K5/1534 ,  G04F10/00

Abstract: A method determines a pin-to-pin delay between clock signals having integrally related frequencies. The method includes generating a delay code corresponding to a delay between a first signal edge of a first clock signal received by a first node of an integrated circuit and a second signal edge of a second clock signal received by a second node of the integrated circuit. The delay code is based on a first time code corresponding to the first signal edge, a second time code corresponding to the second signal edge, a first skew code, a second skew code, and a period of the first clock signal or the second clock signal. The first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is integrally related to the first frequency.