公开(公告)号：US20220197835A1

公开(公告)日：2022-06-23

申请号：US17690535

申请日：2022-03-09

Applicant: Silicon Motion, Inc.

Inventor： An-Pang LI

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

Abstract: A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to the system memory and, accordingly, asserts a flag in the system memory. Through a flag reading channel provided by a interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a data reading channel provided by the interconnect bus, without being delayed by the status checking of the flag. The interconnect bus further provides a flag writing channel and a data writing channel.

公开(公告)号：US20210181972A1

公开(公告)日：2021-06-17

申请号：US17010420

申请日：2020-09-02

Applicant: Silicon Motion, Inc.

Inventor： An-Pang LI

IPC: G06F3/06 ,  G06F13/28

Abstract: The invention introduces a method for programming data of page groups into flash units to include steps for: obtaining, by a host interface (I/F) controller, user data of a page group from a host side, wherein the page group comprises multiple pages; storing, by the host I/F controller, the user data on the pages in a random access memory (RAM) through a bus architecture, outputting the user data on the pages to an engine via an I/F, and enabling the engine to calculate a parity of the page group according to the user data on the pages; obtaining, by a direct memory access (DMA) controller, the parity of the page group from the engine and storing the parity of the page group in the RAM through the bus architecture; and obtaining, by a flash I/F controller, the user data on the pages and the parity of the page group from the RAM through the bus architecture, and programming the user data on the pages and the parity of the page group into a flash module.

公开(公告)号：US20210240642A1

公开(公告)日：2021-08-05

申请号：US17152138

申请日：2021-01-19

Applicant: Silicon Motion, Inc.

Inventor： An-Pang LI

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

Abstract: An efficient control technology for non-volatile memory. In a controller, a host bridge controller and a master computing unit are coupled to a system memory via an interconnect bus, and then coupled to a non-volatile memory interface controller. In response to a read command issued by a host, the non-volatile memory interface controller temporarily stores data read from a non-volatile memory to the system memory and, accordingly, asserts a flag in the system memory. Through a first channel provided by the interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from system memory and returns the data to the host. The master computing unit reads the system memory through a second channel provided by the interconnect bus, without being delayed by the status checking of the flag.

公开(公告)号：US20220197836A1

公开(公告)日：2022-06-23

申请号：US17690555

申请日：2022-03-09

Applicant: Silicon Motion, Inc.

Inventor： An-Pang LI

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

Abstract: A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to a system memory and, accordingly, asserts a flag in the system memory. Through a write channel provided by the interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a read channel provided by the interconnect bus, without being delayed by the status checking of the flag. The host bridge controller executes a data detection command or a preset vendor command to issue a write request for programming data in a virtual address, to trigger a handshake between the host bridge controller and the system memory through the write channel. During the handshake, flag checking is achieved.

公开(公告)号：US20210373798A1

公开(公告)日：2021-12-02

申请号：US17204067

申请日：2021-03-17

Applicant: Silicon Motion, Inc.

Inventor： An-Pang LI

IPC: G06F3/06

Abstract: A technology for controlling non-volatile memory with a multi-stage controller is shown. The multi-stage controller uses an upper on-chip interconnect and a lower on-chip interconnect and includes a serial peripheral bus (SPI) loader, a frond-end central processing unit (FE CPU), and an arbitrator. When being connected to the lower on-chip interconnect, the SPI loader performs code loading for the multi-stage controller. After the SPI loader finishes the code loading, the SPI loader is disconnected from the lower-stage on-chip bus, and the arbitrator connects the FE CPU to the lower on-chip interconnect. This way, the communication channel between the upper on-chip interconnect and the lower on-chip interconnect is not occupied by the FE CPU.