公开(公告)号：US12175086B2

公开(公告)日：2024-12-24

申请号：US18223558

申请日：2023-07-19

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06 ,  G06F12/1009

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.

公开(公告)号：US11449244B2

公开(公告)日：2022-09-20

申请号：US17361227

申请日：2021-06-28

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F12/10 ,  G06F3/06

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.

公开(公告)号：US20220004341A1

公开(公告)日：2022-01-06

申请号：US17306966

申请日：2021-05-04

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06 ,  G06F12/02

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple logical units and a memory controller. The memory controller accesses the memory device and updates content of an activated count table in response to a command issued by a host device. One or more sub-regions to be activated are identified in the command. The activated count table includes a plurality of fields each recording an activated count associated with one sub-region. The memory controller updates content of the activated count table by increasing one or more activated counts associated with the one or more sub-regions identified in the command. The memory controller further selects at least one sub-region according to the content of the activated count table and performs a data rearrangement procedure to move data of the selected at least one sub-region to a first memory space having continuous physical addresses.

公开(公告)号：US20240103732A1

公开(公告)日：2024-03-28

申请号：US18142590

申请日：2023-05-03

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0646 ,  G06F3/0653 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

公开(公告)号：US11636042B2

公开(公告)日：2023-04-25

申请号：US17246707

申请日：2021-05-02

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F12/1009

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and update content of a sub-region bit table in response to a write operation of the active memory block. The sub-region bit table includes one or more bits, each bit is associated with one or more sub-regions and a value of each bit is initially set to a default value. When data of a first logical address received from the host device is written in the active memory block, the memory controller is configured to determine which sub-region the first logical address belongs to and set the value of the bit associated with the sub-region that the first logical address belongs to to a predetermined value different from the default value.

公开(公告)号：US20240103733A1

公开(公告)日：2024-03-28

申请号：US18223558

申请日：2023-07-19

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0613 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/1009

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.

公开(公告)号：US11636030B2

公开(公告)日：2023-04-25

申请号：US17306976

申请日：2021-05-04

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F12/02 ,  G06F13/16

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller updates content of a read count table in response to a read command with a transfer length greater than 1 for designating more than one logical address to be read. The read count table includes multiple fields recording a read count associated with one sub-region and content of the read count table is updated by increasing the read count(s) associated with the sub-region(s) that logical addresses designated in the read command belong to. The memory controller selects at least one sub-region according to the content of the read count table and performs a data rearrangement procedure to move data of the logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.

公开(公告)号：US11614885B2

公开(公告)日：2023-03-28

申请号：US17242332

申请日：2021-04-28

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and accordingly record a plurality of logical addresses in a first mapping table. In response to a determination of recommending for activating one or more sub-regions of the memory device or delivering one or more Host Performance Booster (HPB) entries is required, the memory controller is further configured to update a second mapping table based on the first mapping table before delivering the HPB entries to the host device. The memory controller is further configured to generate the HPB entries according to the second mapping table after the second mapping table has been updated based on the first mapping table and deliver a packet comprising the HPB entries to the host device.

公开(公告)号：US20240103759A1

公开(公告)日：2024-03-28

申请号：US18142579

申请日：2023-05-02

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0607 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. When a sub-region of the memory device is selected based on a predetermined rule to perform a data rearrangement procedure, the memory controller determines whether the selected sub-region is a system data sub-region. When determining that the selected sub-region is not a system data sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses, and when determining that the selected sub-region is a system data sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

公开(公告)号：US20240103757A1

公开(公告)日：2024-03-28

申请号：US18204386

申请日：2023-05-31

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a system data sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a system data sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region corresponding to the write command is not a system data sub-region, the memory controller writes the data into the first predetermined memory block.