公开(公告)号：US20220027282A1

公开(公告)日：2022-01-27

申请号：US17494844

申请日：2021-10-06

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Hui Li

IPC: G06F12/0888 ,  G06F3/06

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

公开(公告)号：US11176049B2

公开(公告)日：2021-11-16

申请号：US16821996

申请日：2020-03-17

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Hui Li

IPC: G06F12/08 ,  G06F12/0888 ,  G06F3/06

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

公开(公告)号：US20210294747A1

公开(公告)日：2021-09-23

申请号：US16821996

申请日：2020-03-17

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Hui Li

IPC: G06F12/0888 ,  G06F3/06

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

公开(公告)号：US20200379674A1

公开(公告)日：2020-12-03

申请号：US16423171

申请日：2019-05-28

Applicant: Silicon Motion Inc.

Inventor： Kuan-Hui Li

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/0804 ,  G06F16/22 ,  G06F16/23

Abstract: The present invention provides a flash memory controller, where the flash memory controller includes a read-only memory, a processor and a cache, the read-only memory stores a program code, and the processor executes the program code to perform access a flash memory module. When the processor receives first data from a host, the processor stores the first data into a region of the cache, and the processor builds or updates a binary tree according to the first data, wherein the binary tree is used when the processor receives a read command from the host.

公开(公告)号：US11630780B2

公开(公告)日：2023-04-18

申请号：US17494844

申请日：2021-10-06

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Hui Li

IPC: G06F12/08 ,  G06F12/0888 ,  G06F3/06

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

公开(公告)号：US10990323B2

公开(公告)日：2021-04-27

申请号：US16423171

申请日：2019-05-28

Applicant: Silicon Motion Inc.

Inventor： Kuan-Hui Li

IPC: G06F3/06 ,  G06F12/0804 ,  G06F16/22 ,  G06F16/23 ,  G06F12/10

Abstract: The present invention provides a flash memory controller, where the flash memory controller includes a read-only memory, a processor and a cache, the read-only memory stores a program code, and the processor executes the program code to perform access a flash memory module. When the processor receives first data from a host, the processor stores the first data into a region of the cache, and the processor builds or updates a binary tree according to the first data, wherein the binary tree is used when the processor receives a read command from the host.

公开(公告)号：US11372589B2

公开(公告)日：2022-06-28

申请号：US16952098

申请日：2020-11-19

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Hui Li ,  Shang-Ta Yang

IPC: G06F3/06 ,  G06F9/30 ,  G06F11/07 ,  G06F12/02

Abstract: A method used in a flash memory controller includes: using a watchdog timer to automatically count a number and to generate a reset trigger signal to a processor if the number counted by the watchdog timer is higher than a threshold; after receiving the reset trigger signal from the watchdog timer, using the processor to copy registry information from at least one of processor, flash memory interface controller, and protocol controller, and then to control the memory controller to write the copied registry information into the dynamic random access memory device without rebooting a system of the flash memory controller.

公开(公告)号：US20210072924A1

公开(公告)日：2021-03-11

申请号：US16952098

申请日：2020-11-19

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Hui Li ,  Shang-Ta Yang

IPC: G06F3/06 ,  G06F11/07 ,  G06F9/30

Abstract: A method used in a flash memory controller includes: using a watchdog timer to automatically count a number and to generate a reset trigger signal to a processor if the number counted by the watchdog timer is higher than a threshold; after receiving the reset trigger signal from the watchdog timer, using the processor to copy registry information from at least one of processor, flash memory interface controller, and protocol controller, and then to control the memory controller to write the copied registry information into the dynamic random access memory device without rebooting a system of the flash memory controller.

公开(公告)号：US10437737B2

公开(公告)日：2019-10-08

申请号：US15869867

申请日：2018-01-12

Applicant: Silicon Motion, Inc.

Inventor： Chien-Chung Chung ,  Kuan-Hui Li ,  Yi-Chang Huang

IPC: G06F12/1009 ,  G06F12/02

Abstract: A data storage device includes a flash memory and a flash memory controller. The flash memory controller operates the flash memory to store data, and stores a mapping table to record the mapping information between a plurality of logical addresses and a plurality of physical addresses of the flash memory. The mapping table is divided into a plurality of groups. Some of the groups are categorized into a first type of trim group and some of the logical addresses of each of the groups of the first type of trim group are included in a trim command. The flash memory controller performs the trim on the groups of the first type of trim group.