公开(公告)号：US20240361919A1

公开(公告)日：2024-10-31

申请号：US18225670

申请日：2023-07-24

申请人： Silicon Motion, Inc.

发明人： Fu-Jen Shih

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0632 ,  G06F3/0653 ,  G06F3/0673

摘要： An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit. The compensation control mechanism operation logic includes a subset handle interface which generates a subset read control signal and transmits the subset read control signal to a corresponding storage circuit.

公开(公告)号：US20240345918A1

公开(公告)日：2024-10-17

申请号：US18628831

申请日：2024-04-08

申请人： Silicon Motion, Inc.

发明人： FAHAO LI

IPC分类号： G06F11/10

CPC分类号： G06F11/1016 ,  G06F11/1068

摘要： A method of searching for read voltages includes: respectively reading a memory segment through read voltages to obtain a sampling data, wherein the read voltages are composed of pairs of adjacent read voltages, and the memory segment is from a non-volatile flash memory; counting the number of first bits in each sampling data, wherein the numbers of first bits correspond to the read voltages respectively; obtaining number differences of the first bits corresponding to the pairs of adjacent read voltages; calculating a coefficient matrix according to the read voltages and the differences of the number of first bits; calculating fitting values according to the read voltages and the coefficient matrix, wherein the fitting value corresponds to the read voltage respectively; and selecting a read voltage corresponding to a minimum value among the fitting values to read the memory segment to perform an error correction program.

公开(公告)号：US20240329845A1

公开(公告)日：2024-10-03

申请号：US18129028

申请日：2023-03-30

申请人： Silicon Motion, Inc.

发明人： Tsung-Chieh Yang

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  H03M13/45

摘要： The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

公开(公告)号：US12105958B2

公开(公告)日：2024-10-01

申请号：US18094990

申请日：2023-01-10

申请人： Silicon Motion, Inc.

发明人： Tsu-Han Lu ,  Hsiao-Chang Yen

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

摘要： A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends a debug injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of an access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, without controlling a memory cell array of flash memory device generating errors.

公开(公告)号：US20240320142A1

公开(公告)日：2024-09-26

申请号：US18123333

申请日：2023-03-20

申请人： Silicon Motion, Inc.

发明人： Kun-Cheng Lai ,  Yen-Yu Jou

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1016

摘要： The present invention provides a control method of a flash memory controller is disclosed, wherein the flash memory controller is configured to access a flash memory module, and the control method comprising: allocating a memory space within a memory for storing data from the host device; dividing the memory space into a plurality of zone buffers, wherein each of the zone buffers is used to store data corresponding to one zone having an opened state; and for a first zone buffer of the plurality of zone buffers, controlling a first buffer and a second buffer within the first zone buffer to alternately store data of a first zone from the host device and write the data of the first zone to a zoned namespace of the flash memory module.

公开(公告)号：US12067235B2

公开(公告)日：2024-08-20

申请号：US17884581

申请日：2022-08-10

申请人： Silicon Motion, Inc.

发明人： Chen-Hao Chen

IPC分类号： G06F3/00 ,  G06F3/06

CPC分类号： G06F3/0608 ,  G06F3/0629 ,  G06F3/0688

摘要： A data storage device includes multiple storage modules. Each storage module includes a storage which having a memory device and a first memory controller and a second memory controller. The first memory controller is coupled to the memory device for accessing the memory device. The second memory controller is coupled to the storage for accessing the storage. The first memory controller includes a first transmission interface. The second memory controller includes a second transmission interface. The first memory controller and the second memory controller communicate with each other through the first transmission interface and the second transmission interface.

公开(公告)号：US20240241787A1

公开(公告)日：2024-07-18

申请号：US18215796

申请日：2023-06-28

申请人： Silicon Motion, Inc.

发明人： Fu-Jen Shih

IPC分类号： G06F11/10 ,  G06F11/07

CPC分类号： G06F11/1068 ,  G06F11/0772

摘要： An interface circuit includes multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, multiple calibration circuits, a compensation accelerator and a processor. The monitor circuits monitor at least one of an amplitude, a frequency and jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The compensation accelerator collects the monitored results and generates a calibration control signal corresponding to each calibration circuit according to calibration commands. The processor generates the calibration commands based on the monitored results. The calibration circuits perform a corresponding calibration operation on the corresponding signal processing device in response to the calibration control signal to adjust a characteristic value of the signal processing device.

公开(公告)号：US20240241786A1

公开(公告)日：2024-07-18

申请号：US18215181

申请日：2023-06-28

申请人： Silicon Motion, Inc.

发明人： Fu-Jen Shih

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/30

CPC分类号： G06F11/1068 ,  G06F11/076 ,  G06F11/3037

摘要： An interface circuit includes a signal processing circuit including multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, a processor and a calibration circuit. The monitor circuits monitor at least one of an amplitude, a frequency and a jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The processor collects the monitored results and determines a calibration operation based on the monitored results. The calibration circuit is coupled to the processor and at least one signal processing device and performs the calibration operation on the signal processing device to adjust a characteristic value of the signal processing device.

公开(公告)号：US20240241785A1

公开(公告)日：2024-07-18

申请号：US18213907

申请日：2023-06-26

申请人： Silicon Motion, Inc.

发明人： Fu-Jen Shih

IPC分类号： G06F11/10 ,  G06F11/30 ,  G06F13/16 ,  H04L1/20

CPC分类号： G06F11/1068 ,  G06F11/3037 ,  G06F13/1673 ,  H04L1/205

摘要： An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results and includes a compensation control mechanism selection circuit which selects a corresponding compensation control mechanism according to the monitored results and set it as a currently-operating compensation control mechanism to control the hardware circuits to operate in compliance with the currently-operating compensation control mechanism.

公开(公告)号：US20240241647A1

公开(公告)日：2024-07-18

申请号：US18215183

申请日：2023-06-28

申请人： Silicon Motion, Inc.

发明人： Fu-Jen Shih

IPC分类号： G06F3/06 ,  G11C7/10

CPC分类号： G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G11C7/1048 ,  G11C2207/2254

摘要： An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.