公开(公告)号：US12254219B2

公开(公告)日：2025-03-18

申请号：US18361150

申请日：2023-07-28

Applicant: Silicon Motion, Inc.

Inventor： Hsu-Ping Ou ,  Kuang-Ting Tai

IPC: G06F3/06

Abstract: A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.

公开(公告)号：US12254202B2

公开(公告)日：2025-03-18

申请号：US18123336

申请日：2023-03-20

Applicant: Silicon Motion, Inc.

Inventor： Kun-Cheng Lai ,  Yen-Yu Jou

IPC: G06F3/06

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module comprises a plurality of blocks, and the control method comprising: receiving a settling command from a host device; in response to the settling command, configuring at least one portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically comprises a plurality of zones; generating parameter information according to a configuration of the zoned namespace; and transmitting the parameter information to the host device, for the host device uses the parameter information to set the zone.

公开(公告)号：US12253564B2

公开(公告)日：2025-03-18

申请号：US18122747

申请日：2023-03-17

Applicant: Silicon Motion, Inc.

Inventor： Tse-Yen Liu

IPC: G01R31/3177 ,  G01R31/317

Abstract: An electronic device includes a functional circuit, a test mode circuit, and a verification circuit. The verification circuit generates and outputs the test waveform signals into the test mode circuit based on a clock signal provided from the test mode circuit, receives test result waveform signals from the test mode circuit when at least one test operation corresponding to the test pattern signal is performed, and compares the test result waveform signals with target result waveform signals to generate and output a failure result signal into the test mode circuit; the failure result signal is used to indicate whether at least one test bit failure occurs.

公开(公告)号：US20250085877A1

公开(公告)日：2025-03-13

申请号：US18955626

申请日：2024-11-21

Applicant: SILICON MOTION INC.

Inventor： Chao-Kuei HSIEH

IPC: G06F3/06 ,  G06F13/42

Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

公开(公告)号：US20250077085A1

公开(公告)日：2025-03-06

申请号：US18810487

申请日：2024-08-20

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06

Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

公开(公告)号：US20250068561A1

公开(公告)日：2025-02-27

申请号：US18236939

申请日：2023-08-22

Applicant: Silicon Motion, Inc.

Inventor： Jie-Hao Lee ,  Ting-Fong Hsu

IPC: G06F12/02

Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of multi-table checking and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first command from a host device, wherein the first command indicates that reading first data at a first logical address is requested; checking at least one logical-to-physical (L2P) address mapping table to generate a first checking result and starting performing a first read operation according to the first checking result, and checking a temporary physical-to-logical (P2L) address mapping table corresponding to a first active block to generate a second checking result for selectively performing a second read operation according to the second checking result; and returning the first data to the host device, wherein the first data is read according to one of the first checking result and the second checking result.

公开(公告)号：US20250055463A1

公开(公告)日：2025-02-13

申请号：US18928216

申请日：2024-10-28

Applicant: Silicon Motion, Inc.

Inventor： Tien-Hsing Yao ,  Chun-Cheng Lee ,  Sheng-I Hsu

IPC: H03K21/02 ,  G06F1/3234 ,  H03K5/00 ,  H03K21/10 ,  H03K21/40

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

公开(公告)号：US20250053313A1

公开(公告)日：2025-02-13

申请号：US18592458

申请日：2024-02-29

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Chieh Peng ,  Tzu-Yi Yang

IPC: G06F3/06

Abstract: The present invention provides a method for controlling a flash memory module. The flash memory module includes a plurality of dies, each die includes a plurality of blocks, each block includes a plurality of pages, and the method includes the steps of: selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determining whether the first block is a full block or a blank block; and if the first block is not the full block or the blank block, writing dummy data to the first block so that the first block becomes the full block; and erasing the plurality of first blocks in the super block, so that the plurality of first blocks become a plurality of blank blocks.

公开(公告)号：US12225126B2

公开(公告)日：2025-02-11

申请号：US18076615

申请日：2022-12-07

Applicant: Silicon Motion, Inc.

Inventor： Wun-Jhe Wu ,  Po-Hung Chen ,  Chiao-Wen Cheng ,  Jiun-Hung Yu ,  Chih-Wei Liu

IPC: H04L9/06 ,  H04L9/08

Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.

公开(公告)号：US12204763B2

公开(公告)日：2025-01-21

申请号：US18080852

申请日：2022-12-14

Applicant: Silicon Motion, Inc.

Inventor： Chun-Yi Chen ,  Hsiao-Te Chang

IPC: G06F3/00 ,  G06F3/06

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for dynamically updating an optimization read voltage (RV) table. The method includes: obtaining a data-read transaction and replying with the data-read transaction to a host side after listening to a first request for read-performance data, which is issued by the host side, thereby enabling the data-performance transaction to be used in an update of the optimization RV table for a designated memory-cell type; and programming multiple records of an updated optimization RV table for the designated memory-cell type into a designated location of the NAND-flash module after listening to a second request for updating the optimization RV table for the designated memory-cell type, which is issued by the host side. The data-read transaction includes a current environmental parameter of a NAND-flash module, the designated memory-cell type and a bit error rate (BER). Each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.