公开(公告)号：US20190205497A1

公开(公告)日：2019-07-04

申请号：US16049803

申请日：2018-07-30

Applicant: Silicon Motion Inc.

Inventor： Shih-Hsiang Tai

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F3/0484 ,  G06F2217/06 ,  G06F2217/84

Abstract: The present invention provides a circuit design method, wherein the circuit design comprises the steps of: designing a plurality of paths, wherein each path comprises a plurality of elements; determining if the paths have enough timing margin to determine at least one specific path; and replacing at least one specific element within the specific path by a configurable gate array cell, wherein a function of the configurable gate array cell is the same as a function of the specific element.

公开(公告)号：US10943047B2

公开(公告)日：2021-03-09

申请号：US16820640

申请日：2020-03-16

Applicant: Silicon Motion, Inc.

Inventor： Shih-Hsiang Tai

IPC: G06F30/394 ,  G06F30/34 ,  G06F30/392 ,  G06F30/3312 ,  G06F3/0484 ,  G06F111/04 ,  G06F119/12

Abstract: A circuit design method is provided, including the steps of: designing a plurality of paths, wherein each path includes a plurality of elements; determining a specific path of the plurality of paths by performing a timing analysis; replacing the specific element in the specific path with the configurable logic gate array cell; and selectively changing a connection mode of a metal layer to make the configurable logic gate array cell have another function. The timing analysis includes: for each path of the plurality of paths, determining whether a chip area meets a constraint condition and whether a timing violation will occur when a specific element in each path is replaced with a configurable logic gate array cell; and when both conditions are met, determining that path as the specific path.

公开(公告)号：US20200218846A1

公开(公告)日：2020-07-09

申请号：US16820640

申请日：2020-03-16

Applicant: Silicon Motion, Inc.

Inventor： Shih-Hsiang Tai

IPC: G06F30/394 ,  G06F30/34 ,  G06F30/392 ,  G06F30/3312

Abstract: A circuit design method is provided, including the steps of: designing a plurality of paths, wherein each path includes a plurality of elements; determining a specific path of the plurality of paths by performing a timing analysis; replacing the specific element in the specific path with the configurable logic gate array cell; and selectively changing a connection mode of a metal layer to make the configurable logic gate array cell have another function. The timing analysis includes: for each path of the plurality of paths, determining whether a chip area meets a constraint condition and whether a timing violation will occur when a specific element in each path is replaced with a configurable logic gate array cell; and when both conditions are met, determining that path as the specific path.