公开(公告)号：US5996065A

公开(公告)日：1999-11-30

申请号：US831473

申请日：1997-03-31

申请人： Sivakumar Makineni ,  Brian L. Hughes ,  Sunhyuk Kimn ,  Michael Chow ,  Suri Babu Medapati ,  Albert Lo

发明人： Sivakumar Makineni ,  Brian L. Hughes ,  Sunhyuk Kimn ,  Michael Chow ,  Suri Babu Medapati ,  Albert Lo

IPC分类号： G06F7/57 ,  G06F9/38

CPC分类号： G06F9/3875 ,  G06F7/483 ,  G06F9/3826 ,  G06F2207/3884 ,  G06F7/49947

摘要： A microprocessor having a pipelined floating point unit operable to bypass pre-rounded results at clock cycle i and provide the pre-rounded results as an operand for a second instruction at clock cycle i+2. In one embodiment, the pipelined execution unit includes at least a first execution step at clock cycle i, and a second execution step at a clock cycle i+1 and clock cycle i+2. The unit includes a bypass leading from the first execution step at clock cycle i, however, there is no bypass leading from the second execution step at clock cycle i+1. The bypass carries the pre-rounded results from the end of the first execution step to the front end of the pipeline via a latched data path which delays the pre-rounded result one clock cycle.

摘要翻译： 具有流水线浮点单元的微处理器，其可操作以在时钟周期i旁路预翻转结果，并将预翻转结果提供为在时钟周期i + 2处的第二指令的操作数。 在一个实施例中，流水线执行单元至少包括在时钟周期i的第一执行步骤和在时钟周期i + 1和时钟周期i + 2的第二执行步骤。 该单元包括在时钟周期i从第一执行步骤引出的旁路，然而，在时钟周期i + 1处没有从第二执行步骤引出的旁路。 旁路通过锁存的数据路径将从第一执行步骤结束的前一轮结果传送到流水线的前端，该锁存数据路径延迟了一个时钟周期的预循环结果。