公开(公告)号：US07035891B2

公开(公告)日：2006-04-25

申请号：US10228432

申请日：2002-08-27

Applicant: Sivakumar Makineni ,  Gautam B. Doshi

Inventor： Sivakumar Makineni ,  Gautam B. Doshi

IPC: G06F11/16

CPC classification number: G06F11/0751 ,  G06F11/0721

Abstract: A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.

Abstract translation: 提供了一种方法和系统，用于在不使用冗余逻辑的情况下执行整数加减运算的软错误检测。 对于整数加法和减法，补偿逻辑利用算术逻辑单元（ALU）结果和操作数产生补偿值。 补偿值由验证逻辑针对预定值确认，以确定是否发生软错误。 这种补偿逻辑和验证逻辑对整数操作数和ALU产生的结果无冗余的进位传播硬件进行操作。

公开(公告)号：US5880985A

公开(公告)日：1999-03-09

申请号：US735058

申请日：1996-10-18

Applicant: Sivakumar Makineni ,  David Harris ,  Thomas Grutkowski ,  Michael James Morrison

Inventor： Sivakumar Makineni ,  David Harris ,  Thomas Grutkowski ,  Michael James Morrison

IPC: G06F7/52

CPC classification number: G06F7/5338 ,  G06F2207/382

Abstract: In order to multiply operands of different binary lengths using a common combined array, for example to do both 8 bit by 8 bit and 16 bit by 16 bit multiplications, 2.sup.m-1 multiplications are performed, where m is equal to the number of different bit lengths it is desired to multiply. For example, where 8.times.8 bit and 16.times.16 bit multiplications are done, 2 different multiplications are done. Each multiplication is an n.times.n/2.sup.m-1 multiplication, e.g., a 16.times.8 bit multiplication. Sign correction is performed by adding a correction vector or by modifying one of the partial products. The results of the multiplications are added together to obtain a 2 n bit result. Groups of bits from said 2 n result are selected depending on the length of the operands being multiplied.

Abstract translation: 为了使用公共组合阵列对不同二进制长度的操作数进行乘法运算，例如进行8位乘8位和16位乘16位乘法运算，执行2m-1乘法，其中m等于不同位数 希望乘以长度。 例如，在完成8×8位和16×16位乘法的情况下，完成2次不同的乘法。 每个乘法是nxn / 2m-1乘法，例如16×8位乘法。 通过添加校正矢量或通过修改部分乘积之一来执行符号校正。 将乘法的结果相加在一起以获得2 n位结果。 来自所述2n结果的比特组根据被乘以的操作数的长度来选择。

公开(公告)号：US06292886B1

公开(公告)日：2001-09-18

申请号：US09169865

申请日：1998-10-12

Applicant: Sivakumar Makineni ,  Sunnhyuk Kimn ,  Gautam B. Doshi ,  Roger A. Golliver

Inventor： Sivakumar Makineni ,  Sunnhyuk Kimn ,  Gautam B. Doshi ,  Roger A. Golliver

IPC: G06F1716

CPC classification number: G06F9/3885 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3893

Abstract: A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.

Abstract translation: 用于以打包数据格式处理SIMD操作数的系统包括标量FMAC和通过操作数传送模块耦合到寄存器文件的向量FMAC。 对于向量操作，操作数传送模块位将打包操作数的SIMD操作数转换为解包操作数，以供第一执行单元处理。 另一个SIMD操作数由向量执行单元处理。

公开(公告)号：US5996065A

公开(公告)日：1999-11-30

申请号：US831473

申请日：1997-03-31

Applicant: Sivakumar Makineni ,  Brian L. Hughes ,  Sunhyuk Kimn ,  Michael Chow ,  Suri Babu Medapati ,  Albert Lo

Inventor： Sivakumar Makineni ,  Brian L. Hughes ,  Sunhyuk Kimn ,  Michael Chow ,  Suri Babu Medapati ,  Albert Lo

IPC: G06F7/57 ,  G06F9/38

CPC classification number: G06F9/3875 ,  G06F7/483 ,  G06F9/3826 ,  G06F2207/3884 ,  G06F7/49947

Abstract: A microprocessor having a pipelined floating point unit operable to bypass pre-rounded results at clock cycle i and provide the pre-rounded results as an operand for a second instruction at clock cycle i+2. In one embodiment, the pipelined execution unit includes at least a first execution step at clock cycle i, and a second execution step at a clock cycle i+1 and clock cycle i+2. The unit includes a bypass leading from the first execution step at clock cycle i, however, there is no bypass leading from the second execution step at clock cycle i+1. The bypass carries the pre-rounded results from the end of the first execution step to the front end of the pipeline via a latched data path which delays the pre-rounded result one clock cycle.

Abstract translation: 具有流水线浮点单元的微处理器，其可操作以在时钟周期i旁路预翻转结果，并将预翻转结果提供为在时钟周期i + 2处的第二指令的操作数。 在一个实施例中，流水线执行单元至少包括在时钟周期i的第一执行步骤和在时钟周期i + 1和时钟周期i + 2的第二执行步骤。 该单元包括在时钟周期i从第一执行步骤引出的旁路，然而，在时钟周期i + 1处没有从第二执行步骤引出的旁路。 旁路通过锁存的数据路径将从第一执行步骤结束的前一轮结果传送到流水线的前端，该锁存数据路径延迟了一个时钟周期的预循环结果。

公开(公告)号：US5793654A

公开(公告)日：1998-08-11

申请号：US719835

申请日：1996-09-30

Applicant: Gautam B. Doshi ,  Sivakumar Makineni

Inventor： Gautam B. Doshi ,  Sivakumar Makineni

IPC: G06F5/01 ,  G06F7/00 ,  G06F7/42

CPC classification number: G06F5/012

Abstract: A saturating alignment shifter for use in the multiply and accumulate unit in a floating point arithmetic unit of a microprocessor that mimics the ideal model of an infinitely wide shifter. A saturation alignment shifter is provided that, in the case of the operation of A*B.+-.C, saturates at a predetermined shifting increment and, in the case where the mantissa of C is saturated, places the mantissa C in the left most significant bits. After adding C to A*B in a summation unit, the mantissa of A*B ends up in the right most significant bits and a single intervening bit, termed the bubble bit, remains between the mantissa of C and the mantissa of A*B. The bubble bit acts to mimic any intervening bits that would have occurred in the case of an ideal infinitely wide shifter. The new shifter eliminates hardware required for special cases and treats all operations with a single alignment shifter giving a system that is faster and more simple than conventional systems.

Abstract translation: 一种饱和对准移位器，用于微处理器的浮点算术单元中的乘法和累积单元，该微处理器模拟无限宽移位器的理想模型。 提供饱和对准移位器，在A * B +/- C的操作的情况下，以预定的移动增量饱和，并且在C的尾数饱和的情况下，将尾数C置于最左侧 位。 在求和单元中向A * B添加C之后，A * B的尾数最终在最右边的最高有效位，并且称为气泡位的单个中间位保留在C的尾数与A * B的尾数之间 。 气泡位用于模拟在理想的无限宽移位器的情况下将发生的任何中间位。 新的移位器消除了特殊情况下所需的硬件，并使用单个对准移位器处理所有操作，给出比传统系统更快更简单的系统。

公开(公告)号：US5771183A

公开(公告)日：1998-06-23

申请号：US672678

申请日：1996-06-28

Applicant: Sivakumar Makineni

Inventor： Sivakumar Makineni

IPC: G06F5/01 ,  G06F7/485 ,  G06F7/50 ,  G06F7/00 ,  G06F7/38

CPC classification number: G06F7/485 ,  G06F5/012 ,  G06F7/49952

Abstract: Provided is a multi-stage shifter for use in both alignment and normalization shifters that provides faster implementation of the shifting process, requires less hardware and is less complex. One embodiment of the present invention provides a shift controller generating shift controller signals and a multi-stage normalization shifter having distinct multiple stages, coupled to a shift controller and receiving a number for normalization. The multi-stage shifter shifts the input number at predetermined increments at each stage and producing a sticky bit output at each stage that participates in the final sticky bit. These sticky bit outputs are ORed together to produce the final sticky bit. The present invention provides for production of the sticky bit with less hardware without sacrificing performance.

Abstract translation: 提供了一种用于对准和归一化移位器的多级移位器，其提供更快地实现移位过程，需要较少的硬件并且不太复杂。 本发明的一个实施例提供了一种换档控制器，其产生换档控制器信号和具有不同多级的多级归一化换档器，其耦合到换档控制器并接收用于归一化的数字。 多级移位器在每个阶段以预定增量移动输入数，并在参与最终粘性位的每个阶段产生粘性位输出。 这些粘性位输出被合并在一起以产生最终的粘性位。 本发明提供了在不牺牲性能的情况下以更少的硬件生产粘性位。

公开(公告)号：US06378067B1

公开(公告)日：2002-04-23

申请号：US09170132

申请日：1998-10-12

Applicant: Roger Golliver ,  Gautam Doshi ,  Sivakumar Makineni

Inventor： Roger Golliver ,  Gautam Doshi ,  Sivakumar Makineni

IPC: G06F948

CPC classification number: G06F9/3861 ,  G06F7/49905 ,  G06F9/30036

Abstract: A method and apparatus to handle exceptions. The method receives and prioritizes exceptions resulting from executing an instruction on different elements of an operand. The exceptions are reported to an interrupt service register which communicates the exceptions to an exception handler to effectively process the exceptions.

Abstract translation: 一种处理异常的方法和装置。 该方法接收并对来自对操作数的不同元素执行指令的异常进行优先排序。 异常报告给一个中断服务寄存器，它将异常传递给异常处理程序，以有效地处理异常。

公开(公告)号：US06321327B1

公开(公告)日：2001-11-20

申请号：US09223457

申请日：1998-12-30

Applicant: Sivakumar Makineni ,  Sunnhyuk Kimn ,  Gautam B. Doshi ,  Roger A. Golliver

Inventor： Sivakumar Makineni ,  Sunnhyuk Kimn ,  Gautam B. Doshi ,  Roger A. Golliver

IPC: G06F738

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/30192

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

Abstract translation: 提供了一种用于将打包的浮点操作数加载到具有一个或多个相关隐含位的寄存器文件条目中的方法。 打包浮点操作数包括多个组件操作数。 每个组件操作数的有效位和指数位被复制到寄存器条目的相应字段，并且测试指数位以确定组件操作数是否被归一化。 当组件操作数被归一化时，设置与组件操作数相对应的隐式位。

公开(公告)号：US06249798B1

公开(公告)日：2001-06-19

申请号：US08728646

申请日：1996-10-10

Applicant: Roger A. Golliver ,  Michael James Morrison ,  Glenn Colon-Bonet ,  Guatam Bhawandas Doshi ,  Jerome C. Huck ,  Alan Hersh Karp ,  Sivakumar Makineni

Inventor： Roger A. Golliver ,  Michael James Morrison ,  Glenn Colon-Bonet ,  Guatam Bhawandas Doshi ,  Jerome C. Huck ,  Alan Hersh Karp ,  Sivakumar Makineni

IPC: G06F738

CPC classification number: H03M7/24

Abstract: An apparatus, a processor, a computer system and a method may be used to directly transfer and translate data between a memory format in an integer processing unit and a floating point format in a floating point processing unit. Data is stored in integer registers of the integer processing unit in a memory format and is stored in floating point registers of the floating point processing unit in a floating point format. A direct data link is provided between the integer register file of the integer processing unit and the floating point register file of the floating point processing unit. The direct data link includes a logic circuit which translates data between the memory format and the floating point format.

Abstract translation: 可以使用装置，处理器，计算机系统和方法在浮点处理单元中的整数处理单元中的存储器格式和浮点格式之间直接传送和转换数据。 数据以存储格式存储在整数处理单元的整数寄存器中，并以浮点格式存储在浮点处理单元的浮点寄存器中。 在整数处理单元的整数寄存器文件和浮点处理单元的浮点寄存器文件之间提供直接数据链接。 直接数据链路包括在存储器格式和浮点格式之间转换数据的逻辑电路。

公开(公告)号：US6009263A

公开(公告)日：1999-12-28

申请号：US901471

申请日：1997-07-28

Applicant: Roger A. Golliver ,  Gautam Bhagwandas Doshi ,  Jerome C. Huck ,  Alan Hersh Karp ,  Sivakumar Makineni ,  Mike Morrison ,  Glen Colon-Bonet

Inventor： Roger A. Golliver ,  Gautam Bhagwandas Doshi ,  Jerome C. Huck ,  Alan Hersh Karp ,  Sivakumar Makineni ,  Mike Morrison ,  Glen Colon-Bonet

IPC: G06F5/01 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/30112 ,  G06F5/012

Abstract: An emulating agent and method is provided that receives numbers having si, exponents and significands of varying lengths and possibly configured in a variety of incompatible formats and to reformat the numbers into a standard uniform format for uniform arithmetic computations in processors operating with different architectures. In one embodiment, the emulating agent has a three-field superset register configured to receive the sign of a number in a first field, the exponent of a number in a second field and the significand of a number in a third field, regardless of the original format of the number, resulting in a number represented in a standard uniform format for computation. The embodiment also allows high level access to the fields to allow users to control the size of the numbers inserted into the fields.

Abstract translation: 提供了一种仿真代理和方法，其接收具有不同长度的符号，指数和有效值的数字，并且可能以各种不兼容的格式配置，并且将数字重新格式化为用于使用不同架构的处理器中的统一算术计算的标准统一格式。 在一个实施例中，仿真代理具有三场超集合寄存器，其被配置为接收第一字段中的数字的符号，第二字段中的数字的指数和第三字段中的数字的有效数，而不管 原始格式的数字，导致以标准统一格式表示的数字进行计算。 该实施例还允许对字段的高级访问以允许用户控制插入到字段中的数字的大小。