Abstract:
An available bit rate scheduler for asynchronous transfer mode communication of a plurality of cells over a communication network in which each cell is characterized by a virtual circuit communication channel and in which each virtual circuit is characterized by one or more profiles. Each profile has a group of sub-profiles, with each sub-profile having a unique bandwidth allocation component. The scheduler incorporates a profile queue buffer for receiving, pairing and storing the profiles and sub-profiles and, a link list processor coupled to the profile queue buffer to receive the profile, sub-profile pairs. The link list processor detects null profile, sub-profile pairs in the buffer and, over-write them with a selected one of the virtual circuit profile, sub-profile pairs. A valid pending register of length p bits, and a memory are coupled to the link list processor. The memory stores pointers to link lists of virtual circuits associated with each of the profile, sub-profile pairs received by the link list processor. The pointers comprise, for each of the link lists, a head pointer to a first entry in the link list and a next pointer to a virtual circuit in the link list last associated by the link list processor with one of the profile, sub-profile pairs.
Abstract:
A method of scheduling cell transmission over an asynchronous transfer mode communication channel. The channel has a characteristic transmission rate that is related to the system clock frequency .function. and an allowed cell rate ACR expressed as a floating point number having a mantissa m, and an exponent e, where 0.ltoreq.m.ltoreq.511, 0.ltoreq.e.ltoreq.31 and ACR=(1+m/512)*2.sup.e. If m.gtoreq.128 then the reciprocal of the mantissa portion (1+m/512) is evaluated by piece-wise linear approximation of the function: ##EQU1## Otherwise, if m
Abstract translation:一种通过异步传输模式通信信道调度小区传输的方法。 信道具有与系统时钟频率f相关的特征传输速率,以及表示为具有尾数m的浮点数的允许信元速率ACR和指数e,其中0≤m≤511,0 = e = 31,ACR =(1 + m / 512)* 2e。 如果m> / = 128,则尾数部分的倒数(1 + m / 512)通过函数的分段线性近似来估计:否则,如果m <128,则尾数部分通过分段估计 函数的明智的线性近似:然后,调度所选择的单元在相对于所选单元之前发送的单元的传输时间T0的时间T发送,其中T = T0 +(ACR-1)* f 。 本发明的硬件实施例仅需要一个9位二进制补码器,三个11位加法器和用于多路复用/控制的胶合逻辑就可以使用符合ATM论坛流量管理标准的VLSI电路来实现,而不需要硬件划分或 乘法。
Abstract:
An available bit rate scheduling method and apparatus for asynchronous transfer mode communication of a plurality of cells over a network characterized by a system clock frequency f and an allowed cell rate ACR. Each cell belongs to an assigned virtual circuit communication channel which is defined by a set of negotiated traffic parameters. The invention partitions the ACR's of the virtual circuits into a smaller subset of profiles/sub-profiles and conducts a deterministic search to service them. The scheduler incorporates a profile generator for iteratively generating a number p of the profiles by (i) outputting a k*modulo 2.sup.i th one of the profiles during each kth iteration of the profile generator, where 1.ltoreq.i.ltoreq.p and 1.ltoreq.k.ltoreq.p-1; (ii) outputting a null profile during each 2.sup.p th one of the iterations; and, (iii) dispatching the profiles from the profile generator to the profile queue such that a particular profile is dispatched at a time T=T.sub.0 +(1/ACR)*f, where T.sub.0 is the dispatch time of a profile dispatched immediately prior to the particular profile. A profile queue coupled to the profile generator receives and sequentially stores the generated profiles. A virtual circuit processor sequentially receives the profiles from the profile queue and, for each one of the received profiles, dispatches to an output queue all virtual circuits which are characterized by the one received profile.