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    Enhanced integrated rate based available bit rate scheduler
    1.
    发明授权
    Enhanced integrated rate based available bit rate scheduler 失效
    增强的基于集成速率的可用比特率调度器

    公开(公告)号：US06049526A

    公开(公告)日：2000-04-11

    申请号：US916342

    申请日：1997-08-22

    Applicant: Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Wong

    Inventor： Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Wong

    IPC: H04L12/56 ,  H04Q11/04 ,  H04J3/22

    CPC classification number: H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5679 ,  H04L2012/568

    Abstract: An available bit rate scheduler for asynchronous transfer mode communication of a plurality of cells over a communication network in which each cell is characterized by a virtual circuit communication channel and in which each virtual circuit is characterized by one or more profiles. Each profile has a group of sub-profiles, with each sub-profile having a unique bandwidth allocation component. The scheduler incorporates a profile queue buffer for receiving, pairing and storing the profiles and sub-profiles and, a link list processor coupled to the profile queue buffer to receive the profile, sub-profile pairs. The link list processor detects null profile, sub-profile pairs in the buffer and, over-write them with a selected one of the virtual circuit profile, sub-profile pairs. A valid pending register of length p bits, and a memory are coupled to the link list processor. The memory stores pointers to link lists of virtual circuits associated with each of the profile, sub-profile pairs received by the link list processor. The pointers comprise, for each of the link lists, a head pointer to a first entry in the link list and a next pointer to a virtual circuit in the link list last associated by the link list processor with one of the profile, sub-profile pairs.

    Abstract translation: 一种用于在通信网络中的多个小区的异步传输模式通信的可用比特率调度器，其中每个小区的特征在于虚拟电路通信信道，并且其中每个虚拟电路由一个或多个简档表征。 每个配置文件具有一组子配置文件，每个子配置文件具有唯一的带宽分配组件。 调度器包括用于接收，配对和存储简档和子简档的简档队列缓冲器，以及耦合到简档队列缓冲器以接收简档的子配置对的链接列表处理器。 链路列表处理器检测缓冲器中的零配置文件，子配置对，并用虚拟电路配置文件，子配置对中的所选择的一个来对其进行写写。 长度为p比特的有效等待寄存器和存储器耦合到链路列表处理器。 存储器存储指向与链接列表处理器接收的每个简档，子简档对相关联的虚拟电路的链接列表的指针。 所述指针针对每个所述链接列表包括到所述链接列表中的第一条目的头指针，以及指向所述链接列表中最后一个与所述链接列表处理器相关联的虚拟电路的下一个指针，其中所述简档，子简档 对。

    Allowed cell rate reciprocal approximation in rate-based available bit rate schedulers
    2.
    发明授权
    Allowed cell rate reciprocal approximation in rate-based available bit rate schedulers 失效
    基于速率的可用比特率调度器允许的信元速率相互近似

    公开(公告)号：US5751697A

    公开(公告)日：1998-05-12

    申请号：US568347

    申请日：1995-12-06

    Applicant: Sivakumar Radhakrishnan ,  Stephen J. Dabecki

    Inventor： Sivakumar Radhakrishnan ,  Stephen J. Dabecki

    IPC: G06F7/52 ,  G06F7/535 ,  H04L12/56 ,  H04Q11/04 ,  H04L12/24 ,  G06F1/02

    CPC classification number: G06F7/535 ,  H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5684 ,  Y10S370/905

    Abstract: A method of scheduling cell transmission over an asynchronous transfer mode communication channel. The channel has a characteristic transmission rate that is related to the system clock frequency .function. and an allowed cell rate ACR expressed as a floating point number having a mantissa m, and an exponent e, where 0.ltoreq.m.ltoreq.511, 0.ltoreq.e.ltoreq.31 and ACR=(1+m/512)*2.sup.e. If m.gtoreq.128 then the reciprocal of the mantissa portion (1+m/512) is evaluated by piece-wise linear approximation of the function: ##EQU1## Otherwise, if m

    Abstract translation: 一种通过异步传输模式通信信道调度小区传输的方法。 信道具有与系统时钟频率f相关的特征传输速率，以及表示为具有尾数m的浮点数的允许信元速率ACR和指数e，其中0≤m≤511,0 / = 128，则尾数部分的倒数（1 + m / 512）通过函数的分段线性近似来估计：否则，如果m <128，则尾数部分通过分段估计 函数的明智的线性近似：然后，调度所选择的单元在相对于所选单元之前发送的单元的传输时间T0的时间T发送，其中T = T0 +（ACR-1）* f 。 本发明的硬件实施例仅需要一个9位二进制补码器，三个11位加法器和用于多路复用/控制的胶合逻辑就可以使用符合ATM论坛流量管理标准的VLSI电路来实现，而不需要硬件划分或 乘法。

    Available bit rate scheduler
    3.
    发明授权
    Available bit rate scheduler 失效
    可用比特率调度程序

    公开(公告)号：US5706288A

    公开(公告)日：1998-01-06

    申请号：US622398

    申请日：1996-03-27

    Applicant: Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Walden Wong

    Inventor： Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Walden Wong

    IPC: H04L12/56 ,  H04Q11/04 ,  H04J3/22

    CPC classification number: H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5679 ,  H04L2012/568

    Abstract: An available bit rate scheduling method and apparatus for asynchronous transfer mode communication of a plurality of cells over a network characterized by a system clock frequency f and an allowed cell rate ACR. Each cell belongs to an assigned virtual circuit communication channel which is defined by a set of negotiated traffic parameters. The invention partitions the ACR's of the virtual circuits into a smaller subset of profiles/sub-profiles and conducts a deterministic search to service them. The scheduler incorporates a profile generator for iteratively generating a number p of the profiles by (i) outputting a k*modulo 2.sup.i th one of the profiles during each kth iteration of the profile generator, where 1.ltoreq.i.ltoreq.p and 1.ltoreq.k.ltoreq.p-1; (ii) outputting a null profile during each 2.sup.p th one of the iterations; and, (iii) dispatching the profiles from the profile generator to the profile queue such that a particular profile is dispatched at a time T=T.sub.0 +(1/ACR)*f, where T.sub.0 is the dispatch time of a profile dispatched immediately prior to the particular profile. A profile queue coupled to the profile generator receives and sequentially stores the generated profiles. A virtual circuit processor sequentially receives the profiles from the profile queue and, for each one of the received profiles, dispatches to an output queue all virtual circuits which are characterized by the one received profile.

    Abstract translation: 一种用于通过网络异步传输模式通信的可用比特率调度方法和装置，其特征在于系统时钟频率f和允许的小区速率ACR。 每个小区属于由一组协商的业务参数定义的分配的虚拟电路通信信道。 本发明将虚拟电路的ACR分成简档/子简档的较小子集，并进行确定性搜索以对其进行维护。 调度器包括一个简档生成器，用于通过（i）在简档生成器的每个第k次迭代期间输出ak *模2个模型之一来迭代地生成数据p，其中1 i = p和1 < / = k

    Maximal length packets
    4.
    发明申请
    Maximal length packets 有权

    公开(公告)号：US20060168384A1

    公开(公告)日：2006-07-27

    申请号：US10977230

    申请日：2004-10-29

    Applicant: Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  Sin Tan ,  Suneeta Sah

    Inventor： Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  Sin Tan ,  Suneeta Sah

    IPC: G06F13/24

    CPC classification number: G06F13/385

    Abstract: Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.

    Method, apparatus and system to generate an interrupt by monitoring an external interface
    6.
    发明授权
    Method, apparatus and system to generate an interrupt by monitoring an external interface 有权
    通过监视外部接口产生中断的方法，装置和系统

    公开(公告)号：US07386640B2

    公开(公告)日：2008-06-10

    申请号：US11025381

    申请日：2004-12-28

    Applicant: David C. Lee ,  Steve Kulick ,  Sivakumar Radhakrishnan

    Inventor： David C. Lee ,  Steve Kulick ,  Sivakumar Radhakrishnan

    IPC: G06F3/00

    CPC classification number: G06F13/22 ,  G06F13/24

    Abstract: In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.

    Abstract translation: 在一些实施例中，呈现通过监视外部接口来产生中断的方法，装置和系统。 在这方面，引入一个中断代理程序通过串行接口与输入/输出（I / O）扩展器进行通信，并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。

    Dynamic squelch detection power control
    9.
    发明授权
    Dynamic squelch detection power control 失效
    动态静噪检测功率控制

    公开(公告)号：US08352764B2

    公开(公告)日：2013-01-08

    申请号：US12286188

    申请日：2008-09-29

    Applicant: Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

    Inventor： Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括用于静噪检测电路的功率控制逻辑，以使得能够以低功率模式选择性地启用互连接口的一个或多个静噪检测电路。 逻辑可以包括静噪模式控制寄存器以选择第一模式或第二模式的功率控制;第二寄存器，耦合到静噪模式控制寄存器以接收软件设置，以指示哪个静噪检测电路在低电平中禁用 互连的功率状态，以及用于在第二模式中动态地检测互连的逻辑通道零点的检测器。 描述和要求保护其他实施例。

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