公开(公告)号：US20240234322A1

公开(公告)日：2024-07-11

申请号：US18609760

申请日：2024-03-19

Applicant: Socionext Inc.

Inventor： Hayato SHINOHARA

IPC: H01L23/528 ,  H01L27/118

CPC classification number: H01L23/5286 ,  H01L27/11803

Abstract: In a semiconductor integrated circuit device, a plurality of standard cells arranged in an X direction include a first standard cell having a logical function and including a transistor having a channel portion extending in the X direction, and a second standard cell including a signal line placed to extend in the X direction. The signal line is formed in a buried interconnect layer, and has an overlap with the channel portion at a position in a Y direction.