公开(公告)号：US20230299070A1

公开(公告)日：2023-09-21

申请号：US18323244

申请日：2023-05-24

Applicant: Socionext Inc.

Inventor： Kengo TAKAHASHI ,  Yuji TAKAHASHI

IPC: H01L27/02 ,  H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/10

Abstract: A designing method of a semiconductor integrated circuit device includes: arranging a plurality of macros within a circuit arrangement area of a semiconductor integrated circuit device in which a plurality of power switch circuits are to be arranged in accordance with a first rule; detecting a narrow area from a first area, a width of the narrow area being less than a first value, the first area being an area in which the macros are not arranged within the circuit arrangement area; arranging the power switch circuits in the detected narrow area in accordance with a second rule different from the first rule; and arranging the power switch circuits in an area other than the narrow area within the first area in accordance with the first rule.