公开(公告)号：US20240213770A1

公开(公告)日：2024-06-27

申请号：US18596231

申请日：2024-03-05

Applicant: Socionext Inc.

Inventor： Hidetoshi TANAKA ,  Yuko NAGAI

IPC: H02H9/04 ,  H01L23/522

CPC classification number: H02H9/046 ,  H01L23/5228

Abstract: An IO cell includes an output circuit having an ESD protection diode, a protective resistance, and an output transistor. The protective resistance is constituted by a plurality of resistor elements formed in a first interconnect layer that is formed in an interconnect process (back end of line (BEOL)). The resistor elements are connected to interconnects formed in a second interconnect layer through vias. In the second interconnect layer, first power supply lines supplying first power are formed above the ESD protection diode. The first power supply lines have overlaps at positions in the X direction with the resistor elements.