公开(公告)号：US20240120240A1

公开(公告)日：2024-04-11

申请号：US18546210

申请日：2022-01-28

Applicant: Soitec

Inventor： YoungPil Kim

IPC: H01L21/66 ,  H01L21/02

CPC classification number: H01L22/26 ,  H01L21/02381 ,  H01L21/02532 ,  H01L22/12 ,  H01L21/0262

Abstract: A setup method for an epitaxy process intended to form a useful layer on a receiving substrate, comprising:



a) selecting a test substrate:

having a thickness less than a usual thickness for a given substrate diameter, and/or
having a low interstitial oxygen concentration, and/or
comprising a SOI stack;


b) fixing initial temperature conditions defining temperatures to be applied to areas of the substrate;
c) forming a useful layer on the test substrate by applying the epitaxy process with the initial temperature conditions; then, measuring slip line defects;
d) fixing new temperature conditions;
e) forming a useful layer on a new test substrate of the same type, by applying the epitaxy process with the new temperature conditions; then, measuring slip line defects; and
f) comparing the quantity of slip line defects measured on the test structures and choosing the temperature conditions generating the fewest slip line defects.