公开(公告)号：US20240345966A1

公开(公告)日：2024-10-17

申请号：US18293858

申请日：2022-03-04

Applicant: Sony Group Corporation

Inventor： Yuuichi Nakamura

IPC: G06F12/14 ,  G06F12/0871

CPC classification number: G06F12/1466 ,  G06F12/0871 ,  G06F2212/1052

Abstract: An information processing device (100) includes a plurality of CPUs (1), a plurality of cache memories (2) associated with the plurality of CPUs (1), and a main memory (3), each of the plurality of CPUs (1) acquires a lock for exclusively accessing data in the main memory (3), and then accesses the data, data related to access of a corresponding CPU (1) and a lock ID for specifying the lock related to the access are associated and written in a cache 10 line of each of the plurality of cache memories (2), and a cache line of each of the plurality of cache memories (2) is flushed when a CPU (1) other than the corresponding CPU (1) acquires the lock specified based on the lock ID written in the cache line.