GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE GATE DRIVING CIRCUIT
    1.
    发明申请
    GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE GATE DRIVING CIRCUIT 有权
    门驱动电路和具有门驱动电路的显示装置

    公开(公告)号:US20100110047A1

    公开(公告)日:2010-05-06

    申请号:US12508054

    申请日:2009-07-23

    IPC分类号: G06F3/038

    CPC分类号: G09G3/3677 G09G2310/0286

    摘要: An output part outputs a high voltage of a first clock signal as a high voltage of an (m)-th gate signal (‘m’ is a natural number) and a low voltage in response to a high signal of an (m+1)-th gate signal outputted from an (m+1)-th stage. A first maintenance part maintains a control part of the pull-up part at a low voltage in response to an (m−1)-th node signal or an (m+1)-th node signal lower than a high signal of a second clock signal having a phase opposite to the phase of the first clock signal received from an (m−1)-th stage or the (m+1)-th stage. A second maintenance part maintains the low voltage of the (m)-th gate signal in response to the (m−1)-th node signal or the (m+1)-th node signal.

    摘要翻译: 输出部分输出第一时钟信号的高电压作为第(m)门信号('m'是自然数)的高电压,并且响应于(m + 1)的高信号输出低电压 )门信号从第(m + 1)级输出。 第一维护部分响应于第(m-1)个节点信号或低于第二个第(m + 1)个高信号的第(m + 1)个节点信号,将上拉部分的控制部分维持在低电压 时钟信号具有与从第(m-1)或第(m + 1)级接收到的第一时钟信号的相位相反的相位。 响应于第(m-1)个节点信号或第(m + 1)个节点信号,第二维护部分保持第(m)门信号的低电压。