公开(公告)号：US07418582B1

公开(公告)日：2008-08-26

申请号：US10844931

申请日：2004-05-13

申请人： Sorin Iacobovici ,  Daniel Leibholz ,  David J. Greenhill

发明人： Sorin Iacobovici ,  Daniel Leibholz ,  David J. Greenhill

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30043 ,  G06F9/30127 ,  G06F9/30141 ,  G06F9/30189 ,  G06F9/3851

摘要： A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

摘要翻译： 一种用于优化多线程处理器中的寄存器文件层次结构的方法。 该方法包括提供具有多个寄存器文件单元的寄存器文件层次结构，当处理器以多线程模式操作时，将多个寄存器文件单元与相应的线程相关联，并且当处理器处理器以单线程平坦化多个寄存器文件单元时 以单线程模式运行。 寄存器文件单元对应于多线程处理器的线程。

公开(公告)号：US5103393A

公开(公告)日：1992-04-07

申请号：US545857

申请日：1990-06-29

申请人： Jonathan P. Harris ,  Daniel Leibholz ,  Brad Miller

发明人： Jonathan P. Harris ,  Daniel Leibholz ,  Brad Miller

IPC分类号： G06F15/173

CPC分类号： G06F15/17343

摘要： An "n" dimensional mesh-connected massively parallel processing system uses pointers to connect requesting processors to allocated processors, and also, to access the allocated processors. The requesting and allocated processors are connected by (i) storing in the requesting processor or in a system controller a pointer which points to the allocated processors as a group and (ii) storing in each of the allocated processors, in a designated memory location, an assigned-marker, or an identifier which identifies the processor as a member of the identified group. When one or more requesting processors require connection to free processors, a request is sent to each processor in the system asking each of them to determine if it is free. Each of the processors which is free then assigns itself indices relating to its position in the mesh and its position relative to other free processors. Each free processor sends its indices to a rendezvous processor associated with the requesting processors, and the rendezvous processor allocates the free processors to a requesting processor based on the connection requirements of that requesting processor and the indices. If several requesting processors request connection to blocks of free processors, the rendezvous processor allocates non-overlapping blocks by assigning to the requesting processors only those free processors with indices which are modulo the associated connection requirement.

摘要翻译： “n”维网格连接的大规模并行处理系统使用指针将请求处理器连接到分配的处理器，并且还访问分配的处理器。 通过以下方式连接请求和分配的处理器：（i）在请求处理器或系统控制器中存储指向分配的处理器作为一组的指针，以及（ii）在指定的存储器位置中存储在所分配的每个处理器中， 分配的标记或标识处理器作为所识别的组的成员的标识符。 当一个或多个请求处理器需要连接到空闲处理器时，向系统中的每个处理器发送请求，要求每个处理器确定它是否是空闲的。 然后，每个处于空闲状态的处理器分配与其在网格中的位置相关的索引及其相对于其它空闲处理器的位置。 每个空闲处理器将其索引发送到与请求处理器相关联的会合处理器，并且会合处理器基于请求处理器和索引的连接要求将空闲处理器分配给请求处理器。 如果几个请求处理器请求连接到空闲处理器的块，则会合处理器通过向请求处理器分配仅具有对应于相关连接要求的索引的那些空闲处理器来分配非重叠块。

公开(公告)号：US20050038979A1

公开(公告)日：2005-02-17

申请号：US10945710

申请日：2004-09-21

申请人： Timothy Fischer ,  Daniel Leibholz ,  James Farrell

发明人： Timothy Fischer ,  Daniel Leibholz ,  James Farrell

IPC分类号： G06F7/48 ,  G06F7/50 ,  G06F7/52 ,  G06F7/535 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K-2, the number of instructions issued for cycle K-1 and the number of instructions speculatively issued in cycle K-1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K-1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value. A stall signal is generated if the indicative value is less than the encoded number or the predetermined value.

摘要翻译： 在可以从指令队列中排除指令的流水线计算机体系结构中，循环K处的指令队列状态通过在循环K-2期间将队列中的无效指令或空闲行的数量相加在一起而确定， 针对循环K-1发出的指令和在循环K-1中推测发出的产生高速缓存命中的指令的数量，并从总和中减去循环K-1排队的指令数。 结果表示队列周期K中的无效指令的数量。无效条目指令的数量，发出的指令的数量和入队指令的数量优选地被表示为平坦向量，使得通过在一个方向上移位来执行加法 ，而通过在相反方向上移动来执行减法。 将结果与在本周期中排队的指令的数量，编号的数量或预定值进行比较。 如果指示值小于编码数或预定值，则产生失速信号。

公开(公告)号：US06954846B2

公开(公告)日：2005-10-11

申请号：US09924335

申请日：2001-08-07

申请人： Daniel Leibholz ,  Wayne Yamamoto

发明人： Daniel Leibholz ,  Wayne Yamamoto

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/14

CPC分类号： G06F9/3012 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3851

摘要： A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

摘要翻译： 微处理器包括多个寄存器文件。 在单线程模式下，微处理器允许单线程访问多个寄存器文件。 在多线程模式中，每个线程都可以访问相应的寄存器文件。 在多线程模式下，多个线程同时执行。 提供电路和硬件以便于相应的模式并且促进模式之间的转换。