-
1.发明授权Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis 失效在数字电路中采用米勒电容效应的方法进行准确的时序分析公开(公告)号：US07594209B2
公开(公告)日：2009-09-22
申请号：US11741042
申请日：2007-04-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： A method for performing a static timing analysis on a circuit that includes gates and their respective interconnects by incorporating the effect of Miller capacitance on timing. A primitive gate is selected with its respective fan-out gates, interconnects attached to the primitive gate's output and interconnects attached to the output of each respective fan-out gate are determined. Using a metric, it is determined if the Miller capacitance effect of a CMOS gate on timing of its fan-out gate and interconnect timing is significant for each fan-out gate. If yes, the gate is replaced with a nonlinear driver model. If no, the gate is replaced with a fixed or dynamic capacitance. Next, if at least one of the fan-out gates is replaced with the nonlinear driver model, the primitive gate is likewise replaced with its corresponding nonlinear model as well. Then, a nonlinear timing simulation is performed on the circuit to generate voltage waveforms at the output of the primitive gate and the input of its fan-out gates that incorporate the effect of the Miller capacitance. However, if none of the fan-out gates are replaced with the nonlinear driver model, a conventional gate and interconnect timing analysis is preferably performed.
摘要翻译： 通过结合米勒电容对定时的影响，对包含栅极及其各自互连的电路执行静态时序分析的方法。 通过其各自的扇出门选择原始门，确定连接到原始门的输出的互连和连接到每个相应的扇出输出门的输出的互连。 使用度量，确定CMOS门极的米勒电容效应是否对于扇出门和互连时序的定时对于每个扇出门是重要的。 如果是，门被替换为非线性驱动器模型。 如果不是，则门被替换为固定或动态电容。 接下来，如果用非线性驱动器模型代替扇出门中的至少一个，则基本门也同样被其对应的非线性模型所取代。 然后，在电路上执行非线性时序仿真，以在原始栅极的输出端和其扇出门的输入端产生并入米勒电容效应的电压波形。 然而，如果不用非线性驱动器模型替换扇出门，则优选地执行常规的栅极和互连时序分析。
-
2.发明授权Method of using a distinct flow of computational control as a reusable abstract data object 失效使用不同的计算控制流作为可重用抽象数据对象的方法公开(公告)号：US07140018B1
公开(公告)日：2006-11-21
申请号：US09597524
申请日：2000-06-20
CPC分类号： G06F9/3851 , G06F9/544
摘要： A method of parallel processing in which there is first provided a first thread which represents an independent flow of control managed by a program structure, the first thread having two states, a first state processing work for the program structure and a second state undispatched awaiting work to process; and a second thread which represents an independent flow of control managed by a program structure separate from the first thread. The method includes using the second thread to prepare work for the first thread to process and placing the work prepared by the second thread in a queue for processing by the first thread. If the first thread is awaiting work to process when the work prepared by the second thread is placed in the queue, the method includes dispatching the first thread and using it to process the work in the queue. If the first thread is processing other work when the work prepared by the second thread is placed in the queue, the method includes using the first thread to complete processing of the other work, access the work in the queue, and then process the work in the queue.
摘要翻译： 一种并行处理方法，其中首先提供表示由程序结构管理的独立的控制流程的第一线程，第一线程具有两种状态，用于程序结构的第一状态处理工作和第二状态未分派等待工作 加工; 以及第二线程，其表示由与第一线程分离的程序结构管理的独立的控制流。 该方法包括使用第二线程为第一线程准备工作以处理并将由第二线程准备的工作放置在队列中以供第一线程处理。 如果第一个线程正在等待工作，当第二个线程准备的工作被放置在队列中时，该方法包括调度第一个线程并使用它来处理队列中的工作。 如果第一个线程正在处理其他工作，当第二个线程准备的工作被放置在队列中时，该方法包括使用第一个线程来完成其他工作的处理，访问队列中的工作，然后处理工作 队列。
-
3.发明授权Methods and systems for interactive debugging in a mixed computer environment 有权在混合计算机环境中进行交互式调试的方法和系统公开(公告)号：US08943475B2
公开(公告)日：2015-01-27
申请号：US13007744
申请日：2011-01-17
CPC分类号： G06F11/3664
摘要： A method of debugging a computer program across a mixed computing environment is provided. The method includes attaching a first debug module to a first program module of the computer program, where the first program module is operating on a first node; attaching a second debug module to a second program module of the computer program, where the second program module operating a second node of a different computer architecture; and initiating debug functions of at least one of the first debug module and the second debug module through a distant linker.
摘要翻译： 提供了一种跨混合计算环境调试计算机程序的方法。 该方法包括将第一调试模块附接到计算机程序的第一程序模块，其中第一程序模块在第一节点上操作; 将第二调试模块附接到所述计算机程序的第二程序模块，其中所述第二程序模块操作不同计算机架构的第二节点; 以及通过远程链接器启动第一调试模块和第二调试模块中的至少一个的调试功能。
-
4.发明授权High performance non-blocking parallel storage manager for parallel software executing on coordinates 失效高性能非阻塞并行存储管理器，用于在坐标上执行并行软件公开(公告)号：US06507903B1
公开(公告)日：2003-01-14
申请号：US09597525
申请日：2000-06-20
IPC分类号： G06F1202
CPC分类号： G06F9/5016
摘要： A method for allocating memory in a parallel processing computing system in which there is first provided a system memory available for parallel processing and first and second threads, each of the threads representing an independent flow of control managed by a program structure and performing different program tasks. The method includes using the first thread to request memory from the system memory; allocating to the first thread a first pool of memory in excess of the request and associating the memory pool with the second thread; using the second thread to request memory from the system memory; allocating to the second thread a second pool of memory in excess of the request and associating the memory pool with the first thread; using the first thread to request further memory from the second thread; and allocating to the first thread a portion of the second pool of memory from the second thread without making a request to the system memory. Each of the first and second memory pools contains memory portions marked by the system memory for the first and second threads. The method then includes freeing by the second thread a portion of the first memory pool marked for the first thread, and allocating to the first thread the portion of the second memory pool marked for the second thread.
摘要翻译： 一种在并行处理计算系统中分配存储器的方法，其中首先提供可用于并行处理的系统存储器以及第一和第二线程，每个线程表示由程序结构管理的独立的控制流程并且执行不同的程序任务 。 该方法包括：使用第一线程从系统存储器请求存储器; 向所述第一线程分配超过所述请求的第一存储器池并将所述存储器池与所述第二线程相关联; 使用第二线程从系统存储器请求存储器; 向所述第二线程分配超过所述请求的第二存储池并将所述存储池与所述第一线程相关联; 使用第一线程从第二线程请求进一步的存储器; 以及从第二线程向第一线程分配第二存储器池的一部分而不向系统存储器发出请求。 第一和第二存储器池中的每一个包含由第一和第二线程的系统存储器标记的存储器部分。 该方法然后包括由第二线程释放标记为第一线程的第一存储器池的一部分，并且向第一线程分配标记为第二线程的第二存储器池的部分。
-
5.发明授权Methods and systems for delegating work objects across a mixed computer environment 有权通过混合计算机环境委派工作对象的方法和系统公开(公告)号：US09235458B2
公开(公告)日：2016-01-12
申请号：US12985887
申请日：2011-01-06
CPC分类号： G06F9/547
摘要： A method of delegating work of a computer program across a mixed computing environment is provided. The method includes: performing on one or more processors: allocating a container structure on a first context; delegating a new operation to a second context based on the container; receiving the results of the new operation; and storing the results in the container.
摘要翻译： 提供了一种在混合计算环境下委托计算机程序的工作的方法。 该方法包括：在一个或多个处理器上执行：在第一上下文上分配容器结构; 基于容器将新操作委托给第二上下文; 收到新业务的结果; 并将结果存储在容器中。
-
6.发明申请METHODS AND SYSTEMS FOR INTERACTIVE DEBUGGING IN A MIXED COMPUTER ENVIRONMENT 有权混合计算机环境中交互式调试的方法和系统公开(公告)号：US20120185828A1
公开(公告)日：2012-07-19
申请号：US13007744
申请日：2011-01-17
IPC分类号： G06F9/44
CPC分类号： G06F11/3664
摘要： A method of debugging a computer program across a mixed computing environment is provided. The method includes attaching a first debug module to a first program module of the computer program, where the first program module is operating on a first node; attaching a second debug module to a second program module of the computer program, where the second program module operating a second node of a different computer architecture; and initiating debug functions of at least one of the first debug module and the second debug module through a distant linker.
摘要翻译： 提供了一种跨混合计算环境调试计算机程序的方法。 该方法包括将第一调试模块附接到计算机程序的第一程序模块，其中第一程序模块在第一节点上操作; 将第二调试模块附接到所述计算机程序的第二程序模块，其中所述第二程序模块操作不同计算机架构的第二节点; 以及通过远程链接器启动第一调试模块和第二调试模块中的至少一个的调试功能。
-
公开(公告)号：US07650246B2
公开(公告)日：2010-01-19
申请号：US11162200
申请日：2005-08-31
CPC分类号： G01R31/31725
摘要： A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.
摘要翻译： 一种用于确定由具有不同接地或电源电压的驱动门驱动的栅极的延迟的方法和装置。 该方法包括从驱动栅极及其驱动栅极的电源和地电压确定经调整的电源电压值，并将调整的电源电压值作为单个电压参数应用于驱动栅极的预定义延迟模型。 该设备的结构是执行该方法。
-
公开(公告)号：US06832378B1
公开(公告)日：2004-12-14
申请号：US09597523
申请日：2000-06-20
IPC分类号： G06F946
CPC分类号： G06F9/4843
摘要： A computer memory structure for parallel computing has a first level of hierarchy comprising a plane. The plane contains a thread which represents an independent flow of control managed by a program structure, a heap portion for data structure, a stack portion for function arguments, and local variables and global data accessible by any part of the program structure. The memory structure further has a second level of hierarchy comprising a space. The space contains two or more of the planes, with the planes in the space containing the program structure. The space further contains common data accessible by the program structure between each of the planes. A third level of hierarchy in the memory structure comprises two or more of the spaces. The spaces contain the same or different program structures, and common data accessible by the program structure between each of the spaces. The program structure comprises a library of programs and further includes a function table for each space, with the function table being adapted to exchange services with the library in each space.
摘要翻译： 用于并行计算的计算机存储器结构具有包括平面的第一层级。 该平面包含一个线程，该线程表示由程序结构管理的独立的控制流，用于数据结构的堆部分，用于函数参数的堆栈部分，以及程序结构的任何部分可访问的局部变量和全局数据。 存储器结构还具有包括空间的第二层级。 空间包含两个或多个平面，空间中的平面包含程序结构。 该空间还包含可通过每个平面之间的程序结构访问的公共数据。 存储器结构中的第三级别的层次结构包括两个或更多个空格。 这些空格包含相同或不同的程序结构，以及通过每个空格之间的程序结构可访问的通用数据。 程序结构包括程序库，并且还包括用于每个空间的功能表，其中该功能表适于与每个空间中的库交换服务。
-
9.发明授权公开(公告)号：US09052968B2
公开(公告)日：2015-06-09
申请号：US13007751
申请日：2011-01-17
CPC分类号： G06F8/54 , G06F8/41 , G06F9/44521
摘要： A method of linking a computer program across a mixed computing environment is provided. The method includes, performing on one or more processors: identifying signatures of elements of the computer program; loading a plurality of modules of the computer program; and linking the plurality of modules using the signatures of the elements.
摘要翻译： 提供了一种在混合计算环境中连接计算机程序的方法。 该方法包括：在一个或多个处理器上执行：识别计算机程序的元素的签名; 加载计算机程序的多个模块; 以及使用所述元素的签名来链接所述多个模块。
-
10.发明申请METHODS AND SYSTEMS FOR LINKING OBJECTS ACROSS A MIXED COMPUTER ENVIRONMENT 有权用于连接混合计算机环境中的对象的方法和系统公开(公告)号：US20120185837A1
公开(公告)日：2012-07-19
申请号：US13007751
申请日：2011-01-17
IPC分类号： G06F9/44
CPC分类号： G06F8/54 , G06F8/41 , G06F9/44521
摘要： A method of linking a computer program across a mixed computing environment is provided. The method includes, performing on one or more processors: identifying signatures of elements of the computer program; loading a plurality of modules of the computer program; and linking the plurality of modules using the signatures of the elements.
摘要翻译： 提供了一种在混合计算环境中连接计算机程序的方法。 该方法包括：在一个或多个处理器上执行：识别计算机程序的元素的签名; 加载计算机程序的多个模块; 以及使用所述元素的签名来链接所述多个模块。
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.016 秒)
