公开(公告)号：US20180052204A1

公开(公告)日：2018-02-22

申请号：US15556652

申请日：2016-01-04

申请人： State Nuclear Power Automation System Engineering Co., Ltd.

发明人： QUNXING JIANG ,  XIAOKAI WANG ,  SHENGJIAN SI ,  YUSEN PEI ,  HUAIYU ZHU ,  TAO YE ,  BING ZHOU ,  TENG SHI

IPC分类号： G01R31/317

CPC分类号： G01R31/31725 ,  G01R29/0273 ,  G01R31/31727 ,  G01R31/318519

摘要： An FPGA clock signal self-detection method relates to the technical field of control module, and the technical problem to be solved is to improve operational reliability and safety of the FPGA chip. The method comprises introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal for correctness. The method of the invention is particularly applicable to a system with the FPGA chip as a main controller or important control unit.