公开(公告)号：US20240188918A1

公开(公告)日：2024-06-13

申请号：US18065385

申请日：2022-12-13

申请人： Analog Devices, Inc.

发明人： Sunrita PODDAR ,  Patrick S. RIEHL ,  Matthew A. WOODRUFF

IPC分类号： A61B6/00 ,  G01R29/027

CPC分类号： A61B6/5258 ,  G01R29/0273 ,  A61B2560/0223

摘要： One embodiment is a method of deconvolving overlapping first and second pulses in a photon-counting CT scanning system, the method comprising detecting a first pulse event having a first detected level; detecting a second pulse event having a second detected level; determining an amount of time that elapses between the detected first pulse event and the detected second pulse event; and reconstructing the first pulse and the second pulse using the first and second detected levels, the duration of time between the first and second pulse events, and a known pulse shape.

公开(公告)号：US20180052204A1

公开(公告)日：2018-02-22

申请号：US15556652

申请日：2016-01-04

申请人： State Nuclear Power Automation System Engineering Co., Ltd.

发明人： QUNXING JIANG ,  XIAOKAI WANG ,  SHENGJIAN SI ,  YUSEN PEI ,  HUAIYU ZHU ,  TAO YE ,  BING ZHOU ,  TENG SHI

IPC分类号： G01R31/317

CPC分类号： G01R31/31725 ,  G01R29/0273 ,  G01R31/31727 ,  G01R31/318519

摘要： An FPGA clock signal self-detection method relates to the technical field of control module, and the technical problem to be solved is to improve operational reliability and safety of the FPGA chip. The method comprises introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal for correctness. The method of the invention is particularly applicable to a system with the FPGA chip as a main controller or important control unit.

公开(公告)号：US09817047B2

公开(公告)日：2017-11-14

申请号：US14881774

申请日：2015-10-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Keith A. Jenkins

IPC分类号： G01R31/02 ,  G01R29/02 ,  H03K5/13 ,  G01R29/027 ,  H03K5/133 ,  H03K5/00

CPC分类号： G01R29/023 ,  G01R29/0273 ,  H03K5/13 ,  H03K5/133 ,  H03K2005/00019

摘要： Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

公开(公告)号：US20170299642A1

公开(公告)日：2017-10-19

申请号：US15291498

申请日：2016-10-12

申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives

发明人： Nicolas RIBIERE-THARAUD

IPC分类号： G01R29/027 ,  G01R23/18 ,  H01Q5/314 ,  H01Q9/02 ,  H01Q5/25

CPC分类号： G01R29/0273 ,  G01R23/18 ,  G01R29/0814 ,  G01R29/0871 ,  H01Q5/25 ,  H01Q5/314 ,  H01Q9/02 ,  H04B1/71637 ,  H04B17/20 ,  H04B17/21 ,  H04B17/23

摘要： A device for the detection of an ultra wide band signal, including a signal reception circuit, a signal divider circuit to divide the received signal into several frequency sub-bands, a circuit to determine the amplitude and duration of the received signal in each frequency sub-band, a circuit to compare the amplitude of the signal received in each frequency sub-band with an amplitude threshold, a circuit to compare the duration of the signal received in each frequency sub-band with a time threshold, and a decision circuit that determines that the received signal is of the ultra wide band type if the amplitude of the signal received in each frequency sub-band is higher than the amplitude threshold and if the duration of the signal received in each frequency sub-band is less than the time threshold.

公开(公告)号：US09638732B2

公开(公告)日：2017-05-02

申请号：US14892600

申请日：2014-04-23

申请人： ZF Friedrichshafen AG

发明人： Florian Weinl

IPC分类号： G01R29/027 ,  G01R29/02 ,  G01R29/08

CPC分类号： G01R29/0273 ,  G01R29/023 ,  G01R29/0276 ,  G01R29/0892

摘要： A method of assessing a pulse-width-modulated signal in which the pulse-width-modulated signal to be assessed is applied to a first input of a microcontroller and a signal, that depends on the pulse-width-modulated signal being assessed, is applied to a second input of the microcontroller for assessment. The pulse-width-modulated signal being assessed is applied to a voltage divider to produce the signal that depends on the same. For the pulse-width-modulated signal to be assessed and for the signal that depends on the same, in each case, the microcontroller determines a time interval between signal edges of the respective signal, and the signal is assessed on the basis of a difference between the time interval between the signal edges in the pulse-width-modulated signal to be assessed and the time interval between the signal edges in the signal that depends on the same.

公开(公告)号：US20140328466A1

公开(公告)日：2014-11-06

申请号：US14362458

申请日：2012-12-13

申请人： KONINKLIJKE PHILIPS N.V.

发明人： Roland Proksa ,  Ewald Roessl

IPC分类号： G01T1/17 ,  G01N23/04

CPC分类号： A61B6/585 ,  A61B6/4241 ,  A61B6/5205 ,  A61B6/5258 ,  A61B6/582 ,  A61B2560/0223 ,  A61B2560/0238 ,  G01R29/0273 ,  G01R29/033 ,  G01R29/0878 ,  G01R29/24 ,  G01T1/171 ,  G01T1/18 ,  G06F7/64 ,  H01L27/14856 ,  H03K5/1252 ,  H03K5/2463 ,  H03K21/40

摘要： The invention relates to a detection apparatus (12) for detecting photons. The detection apparatus comprises a pile-up determining unit (15) for determining whether detection signal pulses being indicative of detected photons are caused by a pile-up event or by a non-pile-up event, wherein a detection values generating unit (16) generates detection values depending on the detection signal pulses and depending on the determination whether the respective detection signal pulse is caused by a pile-up event or by a non-pile-up event. In particular, the detection values generating unit can be adapted to reject the detection signal pulses caused by pile-up events while generating the detection values. This allows for an improved quality of the generated detection values.

摘要翻译： 本发明涉及一种用于检测光子的检测装置（12）。 检测装置包括：堆积确定单元，用于确定是否由堆积事件或非堆积事件引起检测到的光子的指示的检测信号脉冲，其中检测值生成单元（16） ）根据检测信号脉冲产生检测值，并且取决于各个检测信号脉冲是由堆积事件还是由非堆积事件引起的。 特别地，检测值生成单元可以适于在产生检测值的同时拒绝由堆积事件引起的检测信号脉冲。 这样可以提高产生的检测值的质量。

公开(公告)号：US08065102B2

公开(公告)日：2011-11-22

申请号：US12200914

申请日：2008-08-28

申请人： Shoji Kojima

发明人： Shoji Kojima

IPC分类号： G01R25/00

CPC分类号： G01R29/0273 ,  G01R31/317 ,  G01R31/31922 ,  G01R31/31937

摘要： A pulse width measurement circuit generates a time difference signal that corresponds to the pulse width of the input pulse signal PULSE. A delay circuit delays the input pulse signal PULSE by a predetermined amount, and outputs a start signal. An inverter inverts the input pulse signal PULSE, and outputs a stop signal. A time measurement circuit measures the time difference between a positive edge in the start signal and a positive edge in the stop signal, and outputs a time difference signal that corresponds to the time difference.

摘要翻译： 脉冲宽度测量电路产生对应于输入脉冲信号PULSE的脉冲宽度的时差信号。 延迟电路将输入脉冲信号PULSE延迟预定量，并输出起始信号。 反相器反相输入脉冲信号PULSE，并输出停止信号。 时间测量电路测量起始信号中的上升沿与停止信号中的上升沿之间的时间差，并输出与时间差对应的时差信号。

公开(公告)号：US20100171528A1

公开(公告)日：2010-07-08

申请号：US12294798

申请日：2006-03-27

申请人： Laurent Guillot ,  Kamel Abouda ,  Pierre Turpin

发明人： Laurent Guillot ,  Kamel Abouda ,  Pierre Turpin

IPC分类号： H03K5/19

CPC分类号： G01R29/0273 ,  G06F1/24

摘要： A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time.

摘要翻译： 时钟故障检测电路包括具有提供输入时钟信号的时钟输入的时钟故障检测逻辑，计数器和向计数器提供参考时钟信号的参考时钟输入，用于对多个参考时钟周期进行计数。 计数器包括复位输入，该复位输入被布置成接收由输入时钟信号的至少一个时钟沿产生的连续复位脉冲，以重置计数器的计数器值。 复位前的计数器值用于识别时钟频率误差。 还描述了一种检测时钟故障的方法。 通过使用基于参考时钟周期的计数器值和基于输入信号的时钟沿的复位触发，可以在更短的时间内识别时钟频率误差。

公开(公告)号：US20100052651A1

公开(公告)日：2010-03-04

申请号：US12200914

申请日：2008-08-28

申请人： Shoji Kojima

发明人： Shoji Kojima

IPC分类号： G01R29/02

CPC分类号： G01R29/0273 ,  G01R31/317 ,  G01R31/31922 ,  G01R31/31937

摘要： A pulse width measurement circuit 100 generates a time difference signal S2 that corresponds to the pulse width TH of the input pulse signal PULSE. A delay circuit 12 delays the input pulse signal PULSE by a predetermined amount τd, and outputs a start signal SSTART. An inverter 10 inverts the input pulse signal PULSE, and outputs a stop signal SSTOP. A time measurement circuit 14 measures the time difference τ between a positive edge in the start signal SSTART and a positive edge in the stop signal SSTOP, and outputs a time difference signal S2 that corresponds to the time difference.

摘要翻译： 脉冲宽度测量电路100产生对应于输入脉冲信号PULSE的脉冲宽度TH的时差信号S2。 延迟电路12将输入脉冲信号PULSE延迟预定量τd，并输出开始信号SSTART。 逆变器10使输入脉冲信号PULSE反相，并输出停止信号SSTOP。 时间测量电路14测量起始信号SSTART中的上升沿与停止信号SSTOP中的上升沿之间的时间差τ，并输出与时间差对应的时间差信号S2。

公开(公告)号：US07642767B2

公开(公告)日：2010-01-05

申请号：US11371316

申请日：2006-03-07

申请人： Andre Willis

发明人： Andre Willis

IPC分类号： G01R13/02

CPC分类号： G01R29/0273

摘要： Disclosed herein is a method and apparatus used to the measure duty cycle of a clocking waveform utilizing minimal hardware and achieving high accuracy. This invention utilizes digital sampling of the signal to be measured at a rate that can be significantly lower then the clocking frequency of the signal to be measured. It accomplishes broad-band, multi-frequency use by using a time-varying frequency for the sampling clock to make sure that the sampling clock is asynchronous with the frequency of the clocking signal to be measured. The average ratio of the sampled ones (or zeros) as compared to the total number of samples is then computed to derive the measurement of duty cycle.

摘要翻译： 这里公开了一种方法和装置，用于利用最小的硬件测量时钟波形的占空比，并实现高精度。 本发明利用待测信号的数字采样，其速度可以明显低于待测信号的时钟频率。 它通过对采样时钟使用时变频率来实现宽带，多频率使用，以确保采样时钟与要测量的时钟信号的频率异步。 然后计算与样本总数相比采样（或零）的平均比例，以得出占空比的测量值。