公开(公告)号：US5663674A

公开(公告)日：1997-09-02

申请号：US551267

申请日：1995-05-11

申请人： Stefan Beyer ,  Bruno Scheckel ,  Werner Veit ,  Jean Wilwert

发明人： Stefan Beyer ,  Bruno Scheckel ,  Werner Veit ,  Jean Wilwert

IPC分类号： G05F3/26 ,  G05F3/02

CPC分类号： G05F3/265

摘要： An integrated circuit configuration for generating a reference current by bipolar technology includes a transistor of one conduction type having a control terminal being acted upon by a reference voltage and having a load path. An externally connectable resistor is to be connected between the load path of the transistor and a reference potential. A current mirror configuration has an input side connected between the load path of the transistor and a supply voltage source and has an output for picking up a reference current.

摘要翻译： 用于通过双极技术产生参考电流的集成电路配置包括具有一个控制端子的一种导电类型的晶体管，该控制端子被参考电压作用并具有负载路径。 外部可连接的电阻器连接在晶体管的负载路径和参考电位之间。 电流镜配置具有连接在晶体管的负载路径和电源电压源之间的输入侧，并且具有用于拾取参考电流的输出。

公开(公告)号：US5557649A

公开(公告)日：1996-09-17

申请号：US442790

申请日：1995-05-17

申请人： Bruno Scheckel ,  Stefan Heinen ,  Jean Wilwert ,  Helmut Herrmann

发明人： Bruno Scheckel ,  Stefan Heinen ,  Jean Wilwert ,  Helmut Herrmann

IPC分类号： H03K23/66

CPC分类号： H03K23/667

摘要： A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and a clock input. The output of the second flip-flop is coupled to the data input of the third flip-flop, and the clock inputs of the first, second and third flip-flops are acted upon by a clock signal. A first AND gate is connected upstream of the first flip-flop and has a first input being acted upon by a control signal for switching over the divider ratio, and a second input being acted upon by an inverted signal from the output of the third flip-flop. A second AND gate is connected between the first and second flip-flops and has an output connected to the data input of the second flip-flop, a first input receiving an inverted signal from the output of the first flip-flop, and a second input being acted upon by the inverted signal from the output of the third flip-flop.

摘要翻译： 通过差分技术制造的电路结构，用于通过发射极耦合逻辑对具有4/5的可切换分频比分频的时钟信号包括第一，第二和第三串联连接的触发器，每个具有输出，数据输入和时钟输入 。 第二触发器的输出耦合到第三触发器的数据输入，并且第一，第二和第三触发器的时钟输入由时钟信号作用。 第一与门连接在第一触发器的上游，并且具有由控制信号作用的第一输入，用于切换分频比，并且第二输入由来自第三触发器的输出的反相信号 -flop。 第二AND门连接在第一触发器和第二触发器之间，并且具有连接到第二触发器的数据输入的输出端，第一输入端从第一触发器的输出端接收反相信号， 输入由来自第三触发器的输出的反相信号起作用。