公开(公告)号：US20080295054A1

公开(公告)日：2008-11-27

申请号：US12187464

申请日：2008-08-07

申请人： Stephanie L. Alter ,  Kevin D. Drucker ,  Vishwas Rao ,  Leon Song

发明人： Stephanie L. Alter ,  Kevin D. Drucker ,  Vishwas Rao ,  Leon Song

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

摘要翻译： 描述用于估计具有连接有输入的单元的信号路径的错误时序分析结果的风险的技术。 在电路中识别具有连接输入引脚的单元的信号路径。 运行信号路径的定时分析，以识别通过信号路径的最差情况延迟。 通过连接的输入引脚分析工具估计由于具有连接的输入引脚的单元而导致错误时序分析结果的信号路径的风险。 量化与信号路径相关联的定时故障风险的度量是以一组方程式的形式提供的。 这些方程式被嵌入到允许自动多模式，多功率电压温度分析以识别高风险路径的过程中。

公开(公告)号：US07424693B2

公开(公告)日：2008-09-09

申请号：US11377778

申请日：2006-03-16

申请人： Stephanie L. Alter ,  Kevin D. Drucker ,  Vishwas Rao ,  Leon Song

发明人： Stephanie L. Alter ,  Kevin D. Drucker ,  Vishwas Rao ,  Leon Song

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

摘要翻译： 描述用于估计具有连接有输入的单元的信号路径的错误时序分析结果的风险的技术。 在电路中识别具有连接输入引脚的单元的信号路径。 运行信号路径的定时分析，以识别通过信号路径的最差情况延迟。 通过连接的输入引脚分析工具估计由于具有连接的输入引脚的单元而导致错误时序分析结果的信号路径的风险。 量化与信号路径相关联的定时故障风险的度量是以一组方程式的形式提供的。 这些方程式被嵌入到允许自动多模式，多功率电压温度分析以识别高风险路径的过程中。

公开(公告)号：US08468478B2

公开(公告)日：2013-06-18

申请号：US12187464

申请日：2008-08-07

申请人： Stephanie L. Alter ,  Kevin D. Drucker ,  Vishwas Rao ,  Leon Song

发明人： Stephanie L. Alter ,  Kevin D. Drucker ,  Vishwas Rao ,  Leon Song

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

摘要翻译： 描述用于估计具有连接有输入的单元的信号路径的错误时序分析结果的风险的技术。 在电路中识别具有连接输入引脚的单元的信号路径。 运行信号路径的定时分析，以识别通过信号路径的最差情况延迟。 通过连接的输入引脚分析工具估计由于具有连接的输入引脚的单元而导致错误时序分析结果的信号路径的风险。 量化与信号路径相关联的定时故障风险的度量是以一组方程式的形式提供的。 这些方程式被嵌入到允许自动多模式，多功率电压温度分析以识别高风险路径的过程中。

公开(公告)号：US20070094626A1

公开(公告)日：2007-04-26

申请号：US11377778

申请日：2006-03-16

申请人： Stephanie Alter ,  Kevin Drucker ,  Vishwas Rao ,  Leon Song

发明人： Stephanie Alter ,  Kevin Drucker ,  Vishwas Rao ,  Leon Song

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

摘要翻译： 描述用于估计具有连接有输入的单元的信号路径的错误时序分析结果的风险的技术。 在电路中识别具有连接输入引脚的单元的信号路径。 运行信号路径的定时分析，以识别通过信号路径的最差情况延迟。 通过连接的输入引脚分析工具估计由于具有连接的输入引脚的单元而导致错误时序分析结果的信号路径的风险。 量化与信号路径相关联的定时故障风险的度量是以一组方程式的形式提供的。 这些方程式被嵌入到允许自动多模式，多功率电压温度分析以识别高风险路径的过程中。