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1.发明申请Methods for Measurement and Prediction of Hold-Time and Exceeding Hold Time Limits Due to Cells with Tied Input Pins 有权用于测量和预测由于带有输入引脚的单元的保持时间和超过保持时间限制的方法公开(公告)号：US20080295054A1
公开(公告)日：2008-11-27
申请号：US12187464
申请日：2008-08-07
申请人： Stephanie L. Alter , Kevin D. Drucker , Vishwas Rao , Leon Song
发明人： Stephanie L. Alter , Kevin D. Drucker , Vishwas Rao , Leon Song
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.
摘要翻译： 描述用于估计具有连接有输入的单元的信号路径的错误时序分析结果的风险的技术。 在电路中识别具有连接输入引脚的单元的信号路径。 运行信号路径的定时分析，以识别通过信号路径的最差情况延迟。 通过连接的输入引脚分析工具估计由于具有连接的输入引脚的单元而导致错误时序分析结果的信号路径的风险。 量化与信号路径相关联的定时故障风险的度量是以一组方程式的形式提供的。 这些方程式被嵌入到允许自动多模式，多功率电压温度分析以识别高风险路径的过程中。
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2.发明授权Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins 失效用于测量和预测由于具有连接的输入引脚的单元而导致的保持时间和超过保持时间限制的方法公开(公告)号：US07424693B2
公开(公告)日：2008-09-09
申请号：US11377778
申请日：2006-03-16
申请人： Stephanie L. Alter , Kevin D. Drucker , Vishwas Rao , Leon Song
发明人： Stephanie L. Alter , Kevin D. Drucker , Vishwas Rao , Leon Song
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.
摘要翻译： 描述用于估计具有连接有输入的单元的信号路径的错误时序分析结果的风险的技术。 在电路中识别具有连接输入引脚的单元的信号路径。 运行信号路径的定时分析，以识别通过信号路径的最差情况延迟。 通过连接的输入引脚分析工具估计由于具有连接的输入引脚的单元而导致错误时序分析结果的信号路径的风险。 量化与信号路径相关联的定时故障风险的度量是以一组方程式的形式提供的。 这些方程式被嵌入到允许自动多模式，多功率电压温度分析以识别高风险路径的过程中。
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3.发明授权Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins 有权用于测量和预测由于具有连接的输入引脚的单元而导致的保持时间和超过保持时间限制的方法公开(公告)号：US08468478B2
公开(公告)日：2013-06-18
申请号：US12187464
申请日：2008-08-07
申请人： Stephanie L. Alter , Kevin D. Drucker , Vishwas Rao , Leon Song
发明人： Stephanie L. Alter , Kevin D. Drucker , Vishwas Rao , Leon Song
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.
摘要翻译： 描述用于估计具有连接有输入的单元的信号路径的错误时序分析结果的风险的技术。 在电路中识别具有连接输入引脚的单元的信号路径。 运行信号路径的定时分析，以识别通过信号路径的最差情况延迟。 通过连接的输入引脚分析工具估计由于具有连接的输入引脚的单元而导致错误时序分析结果的信号路径的风险。 量化与信号路径相关联的定时故障风险的度量是以一组方程式的形式提供的。 这些方程式被嵌入到允许自动多模式，多功率电压温度分析以识别高风险路径的过程中。
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4.发明申请公开(公告)号：US20090150707A1
公开(公告)日：2009-06-11
申请号：US12245349
申请日：2008-10-03
CPC分类号： G06F13/4243 , G06F13/4247 , G11C7/10
摘要： A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.
摘要翻译： 描述了存储器系统，其中管理存储器模块之间的数据的传输时间，使得存储器系统中的指定点之间的总体时间延迟保持恒定。 可以单独管理多路总线的每个通道，并且在目的地模块处评估数据帧，而不需要在中间模块处进行去歪斜。 通过在总线串行数据速率的一个或多个次数处操作通过模块的数据路径，可以减少通过可能具有路由数据的转换的模块的数据传播的时间延迟，并且选择采样点 所接收的数据使得容纳由于温度变化或老化引起的时间延迟的变化。
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公开(公告)号：US5591984A
公开(公告)日：1997-01-07
申请号：US490968
申请日：1995-06-15
申请人： Kevin D. Drucker
发明人： Kevin D. Drucker
CPC分类号： G01R31/3004
摘要： An electronic system having a backplane defining a plurality of slots each for demountably holding a respective one of a plurality of plug-in modules. The backplane includes a power trace extending to all of the slots for supplying power to all of the slots and a signal trace for carrying a daisy-chained signal to all of the slots. Associated with each of the slots is an arrangement for selectively bypassing the daisy-chained signal past the slot when no module is present in that slot. The arrangement comprises a controllable signal transmission device coupled to the signal trace for selectively providing a conductive path bypassing the slot and a current sensing switch coupled to a branch of the power trace which extends to the slot. The current sensing switch is responsive to current flow through the power trace to the slot for controlling the transmission device to close the conductive path in the absence of current flow and to open the conductive path in the presence of current flow.
摘要翻译： 一种电子系统，具有限定多个槽的背板，每个槽各自可拆卸地保持多个插入式模块中的相应一个。 背板包括延伸到所有插槽的电力迹线，用于向所有时隙供电，以及用于将菊花链信号携带到所有时隙的信号迹线。 与每个时隙相关联的是当在该时隙中没有模块时，有选择地绕过菊花链信号通过时隙的布置。 该装置包括耦合到信号迹线的可控信号传输装置，用于选择性地提供绕过狭槽的导电路径，以及电流感测开关，耦合到延伸到槽的功率迹线的分支。 电流感测开关响应于通过电力轨迹的电流流到槽，用于控制传输装置在没有电流的情况下关闭导电路径，并且在存在电流的情况下打开导电路径。
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公开(公告)号：US07099330B2
公开(公告)日：2006-08-29
申请号：US10010582
申请日：2001-11-13
CPC分类号： H04L12/5601 , H04L47/24 , H04L47/28 , H04L47/50 , H04L47/521 , H04L47/525 , H04L47/6225 , H04L49/205 , H04L49/254 , H04L49/30 , H04L49/3081 , H04L2012/5649 , H04L2012/5651 , H04L2012/5679
摘要： A scheduling apparatus flexibly integrates guaranteed-bandwidth (GB) and best-effort (BE) flows and comprises a combination of a primary weighted-round-robin (WRR) scheduler (PWS) and a secondary WRR scheduler (SWS). The PWS distributes service to the individual GB flows and determines the amount of service that the BE flow aggregate should receive during each frame. The SWS takes care of fairly distributing the service share of the BE aggregate over the individual BE flows. The scheduling apparatus divides the service frame in two subframes. In the first subframe, the PWS fulfills the bandwidth requirements of the GB flows. In the second subframe, the SWS distributes fair service to the BE flows. For each frame, the duration depends on the amount of bandwidth allocated to the GB flows and on the number of GB flows that are backlogged at the beginning of the frame. The amount of bandwidth globally available to BE flows (i.e., the duration of the second subframe) is dynamically adapted to the backlog state of the GB flows, increasing when the GB-flow activity is low, and decreasing when the GB-flow activity intensifies.
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公开(公告)号：US08112655B2
公开(公告)日：2012-02-07
申请号：US12245349
申请日：2008-10-03
CPC分类号： G06F13/4243 , G06F13/4247 , G11C7/10
摘要： A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.
摘要翻译： 描述了存储器系统，其中管理存储器模块之间的数据的传输时间，使得存储器系统中的指定点之间的总体时间延迟保持恒定。 可以单独管理多路总线的每个通道，并且在目的地模块处评估数据帧，而不需要在中间模块处进行去歪斜。 通过在总线串行数据速率的一个或多个次数处操作通过模块的数据路径，可以减少通过可能具有路由数据的转换的模块的数据传播的时间延迟，并且选择采样点 所接收的数据使得容纳由于温度变化或老化引起的时间延迟的变化。
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公开(公告)号：US20090020608A1
公开(公告)日：2009-01-22
申请号：US12062287
申请日：2008-04-03
IPC分类号： G06K7/06
CPC分类号： G06F13/387 , H05K1/0262 , H05K1/181 , H05K2201/10159
摘要： A memory circuit card is described, where the electrical and physical interface between the circuit card and a motherboard bus is independent of the memory type installed on the circuit card. The power supply voltage provided by the mother board is independent of the memory type, and persistent and non-persistent memory types may be used on a plurality of circuit cards installed on the motherboard. The power status of at least portions of the interfaces of the circuit card may be controlled at a future time based on signals received at an input of circuit card.
摘要翻译： 描述了存储器电路卡，其中电路卡和母板总线之间的电气和物理接口独立于安装在电路卡上的存储器类型。 由母板提供的电源电压独立于存储器类型，并且可以在安装在主板上的多个电路卡上使用持久和非持久存储器类型。 基于在电路卡的输入端接收到的信号，电路卡的接口的至少部分的电源状态可以在未来的时间被控制。
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公开(公告)号：US07075934B2
公开(公告)日：2006-07-11
申请号：US10008425
申请日：2001-11-13
IPC分类号： H04L12/56
CPC分类号： H04L47/28 , H04L47/10 , H04L47/24 , H04L47/41 , H04L47/70 , H04L47/826 , H04L47/828 , Y02D50/30
摘要： A scheduler apparatus provides bandwidth guarantees to individual data packet flows as well as to aggregations of those flows (referred to as “bundles”) in a completely transparent manner, i.e., without using any additional scheduling structure. For each bundle, the scheduler determines the ratio between the bandwidth nominally allocated to the bundle and the sum of the individual bandwidth allocations of the flows that are currently backlogged in the bundle. The scheduler uses that ratio to modulate the timestamp increments that regulate the distribution of bandwidth to the individual flows. In this manner, the greater the ratio for that bundle, the more the bandwidth that each backlogged flow in the bundle receives.
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