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公开(公告)号:US20070258475A1
公开(公告)日:2007-11-08
申请号:US11824958
申请日:2007-07-02
申请人: Stephen Chinn , Gene Ciancaglini , Michael Garofalo , James Hart , Michael Lupinacci , Paul Marichal , John Moores , Guy Oliveira , Salil Parikh , Mark Parquette , William Proulx , Donald Proulx , Michael Rydeen
发明人: Stephen Chinn , Gene Ciancaglini , Michael Garofalo , James Hart , Michael Lupinacci , Paul Marichal , John Moores , Guy Oliveira , Salil Parikh , Mark Parquette , William Proulx , Donald Proulx , Michael Rydeen
IPC分类号: H04L12/28
CPC分类号: H04L47/10 , H04L47/22 , H04L49/30 , H04L49/351 , H04L49/357
摘要: A method and apparatus for a communications network that executes a medium access control (MAC) protocol that permits multiple access to a shared medium or shared switching fabric. The MAC protocol uses a BANDWIDTH_ALLOCATOR to regulate access to the network by sending a permission message to a NODE, allowing it to transmit to a specific set of NODEs for a specific length of time. The medium and switching fabric can carry one or more protocols, each of varying framing format and native bitrate. The switching fabric provides a connection-oriented bufferless data transport service that preserves frame ordering. An illustrative embodiment uses a slotted master/slave time-division multiplexed access (TDMA) scheme to allow flexible provisioning of network bandwidth.
摘要翻译: 一种用于通信网络的方法和装置,其执行允许多次访问共享介质或共享交换结构的介质访问控制(MAC)协议。 MAC协议使用BANDWIDTH_ALLOCATOR通过向NODE发送许可消息来规范对网络的访问,允许其在特定时间段内传输到特定的一组节点。 介质和交换结构可以携带一个或多个协议,每种协议具有变化的帧格式和本地比特率。 交换结构提供了面向连接的无缓冲数据传输服务,保留了帧排序。 说明性实施例使用时隙主/从时分复用接入(TDMA)方案来允许灵活地提供网络带宽。
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公开(公告)号:US06201870B1
公开(公告)日:2001-03-13
申请号:US09036234
申请日:1998-03-06
申请人: Muriel Medard , John D. Moores , Katherine L. Hall , Kristin A. Rauschenbach , Salil Parikh , Agnes H. Chan
发明人: Muriel Medard , John D. Moores , Katherine L. Hall , Kristin A. Rauschenbach , Salil Parikh , Agnes H. Chan
IPC分类号: H04L900
CPC分类号: H04L9/0668
摘要: A pseudorandom sequence generator including a first feedback shift register having at least one input and at least one output and a first controller having an output in communication with the at least one input of the first feedback shift register; the first feedback shift register operating at a first speed S1 and the first controller operating at a second speed S2. In one embodiment the first speed S1 of the first feedback shift register is an integer multiple of the second speed S2 of the first controller. In another embodiment the first feedback shift register includes a shift register having an input, an output, and at least one tap; and a feedback function generator having a first input in communication with the at least one tap of the shift register, a second input in communication with the output of the first controller, and an output in communication with the input of the shift register; the feedback function generator includes at least one feedback function.
摘要翻译: 一种伪随机序列发生器,包括具有至少一个输入和至少一个输出的第一反馈移位寄存器和具有与第一反馈移位寄存器的至少一个输入通信的输出的第一控制器; 第一反馈移位寄存器以第一速度S1操作,第一控制器以第二速度S2操作。 在一个实施例中,第一反馈移位寄存器的第一速度S1是第一控制器的第二速度S2的整数倍。 在另一实施例中,第一反馈移位寄存器包括具有输入,输出和至少一个抽头的移位寄存器; 以及反馈函数发生器,其具有与所述移位寄存器的所述至少一个抽头通信的第一输入,与所述第一控制器的输出通信的第二输入以及与所述移位寄存器的输入通信的输出; 所述反馈函数发生器包括至少一个反馈函数。
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