公开(公告)号：US20240330219A1

公开(公告)日：2024-10-03

申请号：US18740145

申请日：2024-06-11

Applicant: Sony Interactive Entertainment Inc.

Inventor： Roelof Roderick Colenbrander

IPC: G06F13/38 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H04L49/351 ,  H04L67/1097

CPC classification number: G06F13/382 ,  G06F13/1668 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282 ,  H04L49/351 ,  H04L67/1097 ,  G06F2213/0026 ,  G06F2213/3808

Abstract: A network architecture including network storage. The network architecture includes a plurality of streaming arrays, each streaming array including a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture includes a PCI Express (PCIe) fabric configured to provide direct access to the network storage from compute nodes of each of the plurality of streaming arrays, the PCIe fabric including a plurality of array-level PCIe switches, each array-level PCIe switch communicatively coupled to compute nodes of compute sleds of a corresponding streaming array and communicatively coupled to the storage server. The network storage is shared by the plurality of streaming arrays.

公开(公告)号：US12068970B2

公开(公告)日：2024-08-20

申请号：US17537583

申请日：2021-11-30

Applicant: Schneider Electric Industries SAS

Inventor： Maxime Sobocinski ,  Philippe Wilhelm ,  Patrice Jaraudias ,  Assane Sarr

IPC: H04L47/56 ,  G06F13/40 ,  H04L12/40 ,  H04L49/351

CPC classification number: H04L47/56 ,  G06F13/4022 ,  H04L12/40 ,  H04L49/351

Abstract: An industrial system for controlling backplane communication including a cluster manager linked to Input/Output modules via a multipoint low voltage differential signaling, MLVDS, bus through passive base plates. The MLVDS bus contains a transmission line and a reception line for the cluster manager. The transmission line of the MLVDS bus is shared by the Input/Output modules for receiving data transmitted by the cluster manager. The reception line of the MLVDS bus is shared by the Input/Output modules for transmitting data to the cluster manager. The Input/Output modules are synchronized in time with the cluster manager and configured to send data on the reception line of the MLVDS bus at respective scheduled time windows.

公开(公告)号：US20240259233A1

公开(公告)日：2024-08-01

申请号：US18162938

申请日：2023-02-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Shalom ,  Omri Kahalon ,  Adi Horowitz ,  Aviad Yehezkel ,  Liran Liss ,  Rabia Loulou ,  Matty Kadosh

IPC: H04L12/46 ,  H04L12/66 ,  H04L49/351 ,  H04L49/356

CPC classification number: H04L12/4625 ,  H04L12/66 ,  H04L49/351 ,  H04L49/358

Abstract: Systems and methods herein are for one or more processing units to modify a network access layer of an ethernet communication to include a local route header (LRH) of an InfiniBand (IB) communication for transmission over an IB network, the modification further to retain ethernet information of all layers of the ethernet communication or to remove at least one of the layers of the ethernet communication for the IB communication.

公开(公告)号：US20240227844A1

公开(公告)日：2024-07-11

申请号：US18000206

申请日：2022-09-05

Applicant: Baidu USA LLC ,  APOLLO INTELLIGENT DRIVING TECHNOLOGY (BEIJING) CO., LTD.

Inventor： Guoli SHU ,  Kedong XU

IPC: B60W60/00 ,  H04L49/351

CPC classification number: B60W60/001 ,  H04L49/351

Abstract: In an embodiment, an autonomous driving vehicle (ADV) processes a set of sensor data concurrently by both a first computing unit and a second computing unit, wherein the set of sensor data is generated by a sensor. The first computing unit formats the set of sensor data into a set of message data. The second computing unit determines whether the set of sensor data indicates a control path fault. The second computing unit reports the control path fault responsive to determining that the set of sensor data indicates the control path fault.

公开(公告)号：US12021760B2

公开(公告)日：2024-06-25

申请号：US17412699

申请日：2021-08-26

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ,  CSBC Corporation, Taiwan

Inventor： Yu-Wen Huang

IPC: H04L49/25 ,  H04L45/00 ,  H04L45/02 ,  H04W40/02 ,  H04W40/24 ,  H04L49/351 ,  H04W84/12

CPC classification number: H04L49/25 ,  H04L45/02 ,  H04L45/72 ,  H04W40/02 ,  H04W40/24 ,  H04L49/351 ,  H04W84/12

Abstract: A routing establishing method for constructing a routing of a chain network including communication routers, each including a wired communication module, a wireless communication module, and a device configuration file. In a wired exploration procedure, exploration is performed by the source communication router through the wired communication module to obtain a wired communication status between the source and the destination communication routers. In a wireless exploration procedure, exploration is performed by the source communication router through the wireless communication module to obtain a wireless communication status between the source and the destination communication routers. In a routing decision procedure, next hop of the source communication router and whether the transmission routing is through the wired or the wireless communication module are determined and set according to the wired and the wireless communication status. The device configuration file includes device numbers related to relative positions of the communication routers.

公开(公告)号：US12007919B2

公开(公告)日：2024-06-11

申请号：US17755513

申请日：2020-08-13

Applicant: AutoNetworks Technologies, Ltd. ,  Sumitomo Wiring Systems, Ltd. ,  Sumitomo Electric Industries, Ltd.

Inventor： Yuanjun Xian ,  Takeshi Hagihara ,  Makoto Mashita ,  Nobuyuki Kobayashi ,  Takehiro Kawauchi ,  Tatsuya Izumi ,  Akihito Iwata ,  Yusuke Yamamoto

IPC: G06F13/26 ,  G06F13/24 ,  H04W4/48 ,  H04L49/351

CPC classification number: G06F13/24 ,  H04W4/48 ,  H04L49/351

Abstract: An in-vehicle communication device for transmitting and receiving a signal by a predetermined communication protocol related to Ethernet® (registered trademark), the in-vehicle communication device comprising: a control circuit configured to generate transmission data including interrupt data inserted into an inter-frame gap between Ethernet frames; and a PHY unit having a communication circuit configured to convert the transmission data generated by the control circuit into a signal and transmit the signal.

公开(公告)号：US11977502B2

公开(公告)日：2024-05-07

申请号：US16056210

申请日：2018-08-06

Applicant: Schneider Electric Industries SAS

Inventor： Patrice Jaraudias ,  Jean-Jacques Adragna ,  Antonio Chauvet ,  Gary R. Ware

IPC: G06F13/28 ,  G06F13/362 ,  G06F13/40 ,  H04L12/413 ,  H04L49/109 ,  H04L49/351 ,  H04L69/12 ,  H04L69/18

CPC classification number: G06F13/28 ,  G06F13/362 ,  G06F13/4022 ,  H04L12/413 ,  H04L49/109 ,  H04L49/351 ,  H04L69/12 ,  H04L69/18 ,  G06F13/4027

Abstract: A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, thereby providing a single hardware platform that may be used to build various automation devices/equipment implemented in an industrial network, such as controllers, field devices, network communication nodes, etc. The monolithic integrated circuit may comprise at least one application processor core operable to execute an industrial application and Ethernet connectivity/management code, including standard Ethernet connectivity/management code and industrial Ethernet connectivity/management code; a real time processing module configured to support a plurality of industrial Ethernet data link layers; an interface configured to be coupled to an external non volatile memory from which the at least one application processor is configured for execute in place processing; and on-chip RAM having a capacity sufficient to eliminate the need for external RAM in execution by the at least one application processor core of an operating system, the industrial application, and the Ethernet connectivity/management code.

公开(公告)号：US20240126560A1

公开(公告)日：2024-04-18

申请号：US18395697

申请日：2023-12-25

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A.T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  G06F13/28 ,  H04L45/00 ,  H04L47/32 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20240064216A1

公开(公告)日：2024-02-22

申请号：US18374475

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kent C. LUSTED

IPC: H04L69/24 ,  H04L69/324 ,  H04L49/351 ,  H04L49/00

CPC classification number: H04L69/24 ,  H04L69/324 ,  H04L49/351 ,  H04L49/3054

Abstract: Examples described herein relate to a network interface comprising physical medium dependent (PMD) circuitry, the PMD circuitry to during link training of at least one lane consistent with IEEE 802.3, exit to TIME_OUT state during TRAIN_LOCAL state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, during link training for at least one lane consistent with IEEE 802.3, the PMD circuitry is to exit to TIME_OUT state during TRAIN_REMOTE state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, link training consistent with IEEE 802.3 comprises performance of the PMD control function in Section 162.8.11 of IEEE 802.3ck.

公开(公告)号：US20230412365A1

公开(公告)日：2023-12-21

申请号：US18241748

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Thomas E. Willis ,  Brad Burres ,  Amit Kumar

IPC: H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L69/12 ,  H04L69/32 ,  G06F16/25 ,  G06F16/2453 ,  H04L49/9005 ,  G11C8/12 ,  G11C29/02 ,  H04L41/0896 ,  G06F30/34 ,  B25J15/00 ,  G06F1/18 ,  G06F1/20 ,  G06F11/34 ,  G06F15/78 ,  H04L41/5025 ,  H04L67/1008 ,  H05K7/14 ,  H05K7/18 ,  H05K7/20 ,  H04L67/1001 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L41/0893 ,  H04L69/22 ,  H04L69/321 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/00 ,  H04L49/351 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11

CPC classification number: H04L9/0819 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0659 ,  G06F3/0604 ,  G06F9/5044 ,  H04L69/12 ,  H04L69/32 ,  G06F16/25 ,  G06F16/2453 ,  G06F9/5088 ,  H04L49/9005 ,  G11C8/12 ,  G11C29/028 ,  H04L41/0896 ,  G06F3/0605 ,  G06F30/34 ,  B25J15/0014 ,  G06F1/183 ,  G06F1/20 ,  G06F9/505 ,  G06F11/3442 ,  G06F15/7807 ,  G06F15/7867 ,  H04L41/5025 ,  H04L67/1008 ,  H05K7/1489 ,  H05K7/18 ,  H05K7/20209 ,  H05K7/20736 ,  H04L67/1001 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/221 ,  G06F16/2237 ,  G06F16/24553 ,  G06F16/2282 ,  G06F12/023 ,  G06F12/14 ,  G06F13/1663 ,  G06F15/17331 ,  G06F3/0611 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F3/0613 ,  G06F3/0629 ,  G06F9/4494 ,  G06F9/28 ,  G06F15/161 ,  G06F3/0644 ,  G06F3/0683 ,  H04L41/0893 ,  H04L69/22 ,  H04L69/321 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/30 ,  H04L49/351 ,  G06F9/4406 ,  G06F9/4411 ,  G06F9/445 ,  G06F3/0632 ,  G06F3/065 ,  G06F3/0685 ,  G06F3/0673 ,  G06F12/0607 ,  G06F16/2455 ,  G06F16/2365 ,  G06F16/248 ,  G06F16/2255 ,  G06F16/9014 ,  G06F16/119 ,  G06F3/0647 ,  G06F12/06 ,  H04L9/0894 ,  G06F2209/509 ,  G06F9/4401 ,  G06F9/44

Abstract: Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.