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    VARIOUS METHODS AND APPARATUSES FOR ESTIMATING CHARACTERISTICS OF AN ELECTRONIC SYSTEMS DESIGN
    1.
    发明申请
    VARIOUS METHODS AND APPARATUSES FOR ESTIMATING CHARACTERISTICS OF AN ELECTRONIC SYSTEMS DESIGN 有权
    用于估计电子系统设计特性的各种方法和装置

    公开(公告)号：US20100318946A1

    公开(公告)日：2010-12-16

    申请号：US12729509

    申请日：2010-03-23

    申请人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

    发明人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/50 ,  G06F2217/78 ,  G06F2217/84

    摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

    摘要翻译： 描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。 在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

    Various methods and apparatuses for estimating characteristics of an electronic systems design
    2.
    发明授权
    Various methods and apparatuses for estimating characteristics of an electronic systems design 有权
    用于估计电子系统设计特性的各种方法和装置

    公开(公告)号：US08024697B2

    公开(公告)日：2011-09-20

    申请号：US12729509

    申请日：2010-03-23

    申请人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

    发明人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： G06F17/5045 ,  G06F17/50 ,  G06F2217/78 ,  G06F2217/84

    摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

    摘要翻译： 描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。 在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

    Various methods and apparatuses for estimating characteristics of an electronic system's design
    3.
    发明授权
    Various methods and apparatuses for estimating characteristics of an electronic system's design 有权
    用于估计电子系统设计特征的各种方法和装置

    公开(公告)号：US07694249B2

    公开(公告)日：2010-04-06

    申请号：US11398036

    申请日：2006-04-04

    申请人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

    发明人： Stephen Hamilton ,  Ian Andrew Swarbrick ,  Scott Carlton Evans ,  Wolf-Dietrich Weber ,  Jay S. Tomlinson

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5045 ,  G06F17/50 ,  G06F2217/78 ,  G06F2217/84

    摘要： Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

    摘要翻译： 描述了用于估计电子系统设计的时间，面积和功率特性的知识产权（IP）发生器的方法和装置。 IP生成器接收用户提供的文件，该文件具有描述具有多层次结构的IP设计的配置的数据。 IP生成器还接收用户提供的技术参数和数据流信息。 IP生成器根据用户提供的技术参数，数据流信息和配置参数，关联每个IP子组件的估计时序，面积和功率特性。 在将寄存器传输级别（RTL）设计转换为门级电路设计之前，IP生成器通过图形用户界面向用户报告定时，面积和功率估计。

    Method and apparatus for decomposing and verifying configurable hardware
    4.
    发明授权
    Method and apparatus for decomposing and verifying configurable hardware 有权
    用于分解和验证可配置硬件的方法和装置

    公开(公告)号：US07299155B2

    公开(公告)日：2007-11-20

    申请号：US11118044

    申请日：2005-04-29

    申请人： Jeffrey Allen Ebert ,  Ravi Venugopalan ,  Scott Carlton Evans

    发明人： Jeffrey Allen Ebert ,  Ravi Venugopalan ,  Scott Carlton Evans

    IPC分类号： G06F11/30

    CPC分类号： G06F11/26 ,  G01R31/318314 ,  G06F17/5022

    摘要： The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a set of one or more units at a first level of a configurable hardware system design hierarchy into a set of two or more units of a lower level of the hardware system design hierarchy. The set of one or more units at a first level includes one or more units dynamically instantiated at design creation time as well as at least a first unit composed of a previously instantiated hardware system composed with two or more levels of units within the hardware system design hierarchy of the previously instantiated hardware system.

    摘要翻译： 本发明包括用于分解和验证可配置硬件的方法和装置。 在一个实施例中，该方法包括将可配置硬件系统设计层级的第一级别的一个或多个单元的集合自动分解成硬件系统设计层级的较低级别的两个或多个单元的集合。 第一级的一个或多个单元的集合包括在设计创建时刻动态实例化的一个或多个单元以及至少由硬件系统设计中由两个或多个单元级构成的先前实例化的硬件系统组成的第一单元 先前实例化的硬件系统的层次结构。