公开(公告)号：US06895542B2

公开(公告)日：2005-05-17

申请号：US10699649

申请日：2003-11-04

申请人： Sterling Smith ,  Huimin Tsai ,  Sheng-Yao Liu

发明人： Sterling Smith ,  Huimin Tsai ,  Sheng-Yao Liu

IPC分类号： G06F5/06 ,  H04L25/14 ,  H04L25/49 ,  H04N1/40 ,  G06F11/00

CPC分类号： H04L25/14 ,  G06F5/10 ,  H04L25/4908

摘要： A data recovery circuit for use in a data receiving system to recover an m-bit data stream from an n-bit data stream. The data recovery circuit comprises an n-bit data reconstruction circuit for selecting a data boundary in response to a boundary selection signal and producing a reconstructed n-bit data stream based on the boundary data, a FIFO buffer circuit for temporarily storing the reconstructed n-bit data stream and reading out the m-bit data stream, and a detection circuit for detecting whether the m-bit data stream from the FIFO buffer circuit conforms to a predetermined format and thereby producing a boundary selection signal for controlling the data boundary selection of the n-bit data reconstruction circuit.

摘要翻译： 一种数据恢复电路，用于在数据接收系统中从n位数据流中恢复m位数据流。 数据恢复电路包括：n比特数据重构电路，用于响应于边界选择信号选择数据边界，并且基于边界数据产生重建的n位数据流; FIFO缓冲电路，用于临时存储重建的n位数据， 读出m位数据流;检测电路，用于检测来自FIFO缓冲电路的m位数据流是否符合预定格式，从而产生用于控制数据边界选择的边界选择信号 n位数据重建电路。

公开(公告)号：US07310397B2

公开(公告)日：2007-12-18

申请号：US10698623

申请日：2003-11-03

申请人： Sterling Smith ,  Sheng-Yao Liu ,  Huimin Tsai

发明人： Sterling Smith ,  Sheng-Yao Liu ,  Huimin Tsai

IPC分类号： H04L7/00

CPC分类号： H04L7/0331

摘要： In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock pulses is used for sampling approximately the transition portions between every two adjacent data bits in the incoming data stream to produce a second sampled data stream. By detecting the resemblance of each bit in the second sampled data stream to the corresponding two adjacent bits in the first sampled data stream, a phase detection and correction circuit determines an early condition or a late condition for the phases of the sampling clocks and produces a signal to correct the phases of the sampling clocks by shifting the phases backwards or forwards. According to the invention, sampling clocks with lower frequencies can be used for sampling, and the phase error can be corrected to obtain the correct data recovery.

摘要翻译： 在本发明的数据恢复电路中，第一组采样时钟脉冲被用于对输入数据流中的数据位的大部分中心部分采样以产生第一采样数据流，而第二组采样时钟脉冲是 用于对输入数据流中每两个相邻数据位之间的过渡部分进行近似采样，以产生第二采样数据流。 通过检测第二采样数据流中的每一比特相对于第一采样数据流中相应的两个相邻比特，相位检测和校正电路确定采样时钟的相位的早期状态或后期状态，并产生一个 信号通过向后或向后移动相位来校正采样时钟的相位。 根据本发明，可以使用具有较低频率的采样时钟进行采样，并且可以校正相位误差以获得正确的数据恢复。