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    Formation of self-aligned passivation for interconnect to minimize electromigration
    3.
    发明授权
    Formation of self-aligned passivation for interconnect to minimize electromigration 有权
    形成用于互连的自对准钝化，以最小化电迁移

    公开(公告)号：US06309959B1

    公开(公告)日：2001-10-30

    申请号：US09630943

    申请日：2000-08-03

    申请人： Pin-Chin C. Wang ,  Lu You ,  Joffre Bernard ,  Amit Marathe

    发明人： Pin-Chin C. Wang ,  Lu You ,  Joffre Bernard ,  Amit Marathe

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76886 ,  H01L21/76888

    摘要： An interconnect opening of an integrated circuit is filled with a conductive fill with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first conductive material is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The interconnect opening is further filled with a second conductive material by growing the second conductive material from the seed layer to form a conductive fill of the first conductive material and the second conductive material within the interconnect opening. The first conductive material and the second conductive material are comprised of a bulk metal, and at least one of the first conductive material and the second conductive material is a metal alloy having an alloy dopant in the bulk metal. In addition, a plasma treatment process is performed to remove any metal oxide or metal hydroxide from a top surface of the conductive fill. A self-aligned passivation material of an intermetallic compound or a metal oxide is formed at the top surface of the conductive fill with the alloy dopant that segregates out and to the top surface of the conductive fill. The intermetallic compound or the metal oxide is an additional passivation material between the top surface of the conductive fill and a layer of bulk passivation material deposited over the semiconductor wafer to prevent drift of the bulk metal, such as copper, of the conductive fill along a bottom surface of the layer of bulk passivation material.

    摘要翻译： 集成电路的互连开口填充有导电填料，其中互连开口位于半导体晶片上的绝缘层内。 第一导电材料的籽晶层保形地沉积在互连开口的侧壁和底壁上。 通过从种子层生长第二导电材料以形成互连开口内的第一导电材料和第二导电材料的导电填料，互连开口进一步填充有第二导电材料。 第一导电材料和第二导电材料由体金属组成，并且第一导电材料和第二导电材料中的至少一个是在本体金属中具有合金掺杂剂的金属合金。 此外，进行等离子体处理工艺以从导电填料的顶表面去除任何金属氧化物或金属氢氧化物。 在导电填料的顶表面上形成金属间化合物或金属氧化物的自对准钝化材料，其中合金掺杂剂分离出导电填料的顶表面。 金属间化合物或金属氧化物是在导电填料的顶表面和沉积在半导体晶片上的体积钝化材料层之间的另外的钝化材料，以防止导电填料的体金属（例如铜）沿着 底部表面堆积钝化材料层。