摘要:
In a partitioned process environment, storage is reassigned by a shuffle of guest absolute address spaces which may be reassigned among partitions without restriction as to the position of the space to be reassigned relative to the position of the partition to which it is to be assigned. The reassignment is accomplished by adjusting the origin addresses by an adjustment value corresponding to the size of the address space of an additional memory area to be added to a selected partition. Furthermore, the size of the address space of the selected partition is increased by the same adjustment value. The system employs duplicated origin and limit arrays which are used to convert from a partition (guest) absolute address to a system (host) absolute address and uses duplicated configuration arrays by which the system absolute addresses are converted to physical memory addresses. Revised origin and limit information and configuration information is stored in an origin and limit array in the stand by state and in a configuration array in the stand by state. Autonomously operating circuitry is responsive to control signals to temporarily suspend memory commands from the input-output system, to reconfigure the origin and limit arrays and the configuration arrays to enable the system to use the revised information and, thereafter, to resume the processing of memory commands from the input-output system.
摘要:
A response priority circuit arrangement for determining the priority among simultaneous responses from different access-time levels L3 and L2 in a storage hierarchy to maintain nearly the same order among the simultaneous responses as the order of their storage access requests.The storage requests were put into an indexed slot in a hardware queue. The index of the assigned queue slot is sent to a basic storage module (BSM) part of the hierarchy which is selected by the storage address supplied by the processor making the storage request. The selected BSM will have the requested data either in its main memory part (L3) or in its high-speed buffer part (L2).The priority circuit arrangement has a separate group of AND gates for each hierarchy level L3 and L2. The groups are interlocked by a circuit which disables the L2 group if any AND gate is enabled in the L3 group. Only one AND gate can be enabled in both L3 and L2 groups. When simultaneous responses are signalled from the L3 and L2 levels, the L3 gate is given priority since the L3 response resulted from an earlier request than the L2 response. The output of the enabled AND gate indicates the index of the slot in the queue which contains the request matching the response given priority. A bus connection can then be made using that slot's information for the data transfer between the selected BSM and the requesting processor.