公开(公告)号：US20080042705A1

公开(公告)日：2008-02-21

申请号：US11648314

申请日：2006-12-29

申请人： Su Hyun Kim ,  Min Young Yoo

发明人： Su Hyun Kim ,  Min Young Yoo

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/095

摘要： A duty cycle correction (DCC) circuit and a delayed locked loop (DLL) circuit using the same are disclosed. The DCC circuit is operated by an enable signal which is enabled when the DLL is locked. The duty cycle correction (DCC) circuit includes a clock input unit and a duty cycle mixing unit. The clock input unit receives the enable signal and first and second clock input signals having opposite phases, generates an inverting signal of the first clock input signal, and when the enable signal is enabled, generates first and second internal clock signals, based on the first and second clock input signals and the inverting signal. The duty cycle mixing unit mixes a phase of the first internal clock signal with a phase of the second internal clock signal.

摘要翻译： 公开了一种占空比校正（DCC）电路和使用其的延迟锁定环（DLL）电路。 DCC电路由使能信号操作，当DLL被锁定时使能信号被使能。 占空比校正（DCC）电路包括时钟输入单元和占空比混合单元。 时钟输入单元接收使能信号和具有相反相位的第一和第二时钟输入信号，产生第一时钟输入信号的反相信号，并且当使能信号被使能时，基于第一时钟输入信号产生第一和第二内部时钟信号 和第二时钟输入信号和反相信号。 占空比混合单元将第一内部时钟信号的相位与第二内部时钟信号的相位相混合。

公开(公告)号：US07830185B2

公开(公告)日：2010-11-09

申请号：US11648314

申请日：2006-12-29

申请人： Su Hyun Kim ,  Min Young Yoo

发明人： Su Hyun Kim ,  Min Young Yoo

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/095

摘要： A duty cycle correction (DCC) circuit and a delayed locked loop (DLL) circuit using the same are disclosed. The DCC circuit is operated by an enable signal which is enabled when the DLL is locked. The duty cycle correction (DCC) circuit includes a clock input unit and a duty cycle mixing unit. The clock input unit receives the enable signal and first and second clock input signals having opposite phases, generates an inverting signal of the first clock input signal, and when the enable signal is enabled, generates first and second internal clock signals, based on the first and second clock input signals and the inverting signal. The duty cycle mixing unit mixes a phase of the first internal clock signal with a phase of the second internal clock signal.

摘要翻译： 公开了一种占空比校正（DCC）电路和使用其的延迟锁定环（DLL）电路。 DCC电路由使能信号操作，当DLL被锁定时使能信号被使能。 占空比校正（DCC）电路包括时钟输入单元和占空比混合单元。 时钟输入单元接收使能信号和具有相反相位的第一和第二时钟输入信号，产生第一时钟输入信号的反相信号，并且当使能信号被使能时，基于第一时钟输入信号产生第一和第二内部时钟信号 和第二时钟输入信号和反相信号。 占空比混合单元将第一内部时钟信号的相位与第二内部时钟信号的相位相混合。