公开(公告)号：US20060282233A1

公开(公告)日：2006-12-14

申请号：US11139370

申请日：2005-05-26

申请人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

发明人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.

摘要翻译： 计算机系统仿真方法从独立于硬件体系结构的算法实现规范模型开始。 代表硬件组件的高级功能块使用总线架构独立的通用通道连接在一起。 总线架构独立的通用通道用时序和协议细节进行注释，以定义总线架构独立通用通道和表示硬件组件的功能块之间的接口。 该接口被改进以获得用于通信空间的CCATB。 read（）和write（）接口调用被分解成几个对应于总线引脚的方法调用，以获得系统调试和验证的可观察周期精度，并获得周期精确模型。 方法调用被信号替换，并且代表硬件组件的功能块被进一步细化以获得可以手动或自动映射到RTL的引脚/周期精确模型，或者用于与现有的RTL组件共模拟。

公开(公告)号：US07778815B2

公开(公告)日：2010-08-17

申请号：US11139370

申请日：2005-05-26

申请人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

发明人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

IPC分类号： G06F13/12

CPC分类号： G06F17/5022

摘要： A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.

摘要翻译： 计算机系统仿真方法从独立于硬件体系结构的算法实现规范模型开始。 代表硬件组件的高级功能块使用总线架构独立的通用通道连接在一起。 总线架构独立的通用通道用时序和协议细节进行注释，以定义总线架构独立通用通道和表示硬件组件的功能块之间的接口。 该接口被改进以获得用于通信空间的CCATB。 read（）和write（）接口调用被分解成几个对应于总线引脚的方法调用，以获得系统调试和验证的可观察周期精度，并获得周期精确模型。 方法调用被信号替换，并且代表硬件组件的功能块被进一步改进以获得可以手动或自动映射到RTL的引脚/周期精确模型，或者用于与现有RTL组件协同模拟。