公开(公告)号：US20060282233A1

公开(公告)日：2006-12-14

申请号：US11139370

申请日：2005-05-26

申请人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

发明人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.

摘要翻译： 计算机系统仿真方法从独立于硬件体系结构的算法实现规范模型开始。 代表硬件组件的高级功能块使用总线架构独立的通用通道连接在一起。 总线架构独立的通用通道用时序和协议细节进行注释，以定义总线架构独立通用通道和表示硬件组件的功能块之间的接口。 该接口被改进以获得用于通信空间的CCATB。 read（）和write（）接口调用被分解成几个对应于总线引脚的方法调用，以获得系统调试和验证的可观察周期精度，并获得周期精确模型。 方法调用被信号替换，并且代表硬件组件的功能块被进一步细化以获得可以手动或自动映射到RTL的引脚/周期精确模型，或者用于与现有的RTL组件共模拟。

公开(公告)号：US07778815B2

公开(公告)日：2010-08-17

申请号：US11139370

申请日：2005-05-26

申请人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

发明人： Sudeep Pasricha ,  Nikil Dutt ,  Mohamed Ben-Romdhane

IPC分类号： G06F13/12

CPC分类号： G06F17/5022

摘要： A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.

摘要翻译： 计算机系统仿真方法从独立于硬件体系结构的算法实现规范模型开始。 代表硬件组件的高级功能块使用总线架构独立的通用通道连接在一起。 总线架构独立的通用通道用时序和协议细节进行注释，以定义总线架构独立通用通道和表示硬件组件的功能块之间的接口。 该接口被改进以获得用于通信空间的CCATB。 read（）和write（）接口调用被分解成几个对应于总线引脚的方法调用，以获得系统调试和验证的可观察周期精度，并获得周期精确模型。 方法调用被信号替换，并且代表硬件组件的功能块被进一步改进以获得可以手动或自动映射到RTL的引脚/周期精确模型，或者用于与现有RTL组件协同模拟。

公开(公告)号：US09240786B2

公开(公告)日：2016-01-19

申请号：US13794775

申请日：2013-03-11

申请人： Kazuyuki Tanimura ,  Nikil Dutt

发明人： Kazuyuki Tanimura ,  Nikil Dutt

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/096

CPC分类号： H03K19/003 ,  H03K19/00392 ,  H03K19/096

摘要： Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HURL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HURL circuit has a differential power at a level that is resistive to DPA attacks.

摘要翻译： 公开了用于DPA攻击电阻安全电路设计的均匀双轨逻辑。 根据一个实施例，HDRL电路包括主要小区和互补小区，其中所述互补小区是所述主小区的相同副本。 HURL电路包括第一组输入和第二组输入，其中第二组输入是第一组输入的否定。 HURL电路的差分功率在DPA攻击阻力的水平上。

公开(公告)号：US20050193359A1

公开(公告)日：2005-09-01

申请号：US11057416

申请日：2005-02-14

申请人： Rajesh Gupta ,  Sumit Gupta ,  Nikil Dutt ,  Alexandru Nicolau

发明人： Rajesh Gupta ,  Sumit Gupta ,  Nikil Dutt ,  Alexandru Nicolau

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.

摘要翻译： 用于执行数字设计的高级合成（HLS）的方法包括用于对设计的行为描述进行变换的第一阶段和用于从用于变换行为描述的多个变换中选择变换的第二阶段。 该方法还包括用于使用较低级原语实现变换的行为描述的第三阶段，以及用于生成用于设计的实现代码的第四阶段。

公开(公告)号：US07383529B2

公开(公告)日：2008-06-03

申请号：US11057416

申请日：2005-02-14

申请人： Rajesh Kumar Gupta ,  Sumit Gupta ,  Nikil Dutt ,  Alexandru Nicolau

发明人： Rajesh Kumar Gupta ,  Sumit Gupta ,  Nikil Dutt ,  Alexandru Nicolau

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.

摘要翻译： 用于执行数字设计的高级合成（HLS）的方法包括用于对设计的行为描述进行变换的第一阶段和用于从用于变换行为描述的多个变换中选择变换的第二阶段。 该方法还包括用于使用较低级原语实现变换的行为描述的第三阶段，以及用于生成用于设计的实现代码的第四阶段。

公开(公告)号：US08621444B2

公开(公告)日：2013-12-31

申请号：US10599593

申请日：2004-09-30

申请人： Nikil Dutt ,  Mohammad H. Reshadi

发明人： Nikil Dutt ,  Mohammad H. Reshadi

IPC分类号： G06F9/45

CPC分类号： G06F9/45504

摘要： Methods for simulating an instruction set architecture (ISA) with a instruction set simulator (ISS) are provided. One exemplary embodiment of the methods includes fetching a first decoded instruction during a run time, where the decoded instruction is decoded from an original instruction in a target application program during a compile time preceding the run time. The decoded instruction can designate a template configured to implement the functionality of the original instruction. The method also preferably includes determining whether the fetched instruction is modified from the original instruction and then executing the designated template if the instruction was not modified. The method can also include decoding the original instruction during the compile time by selecting a template corresponding to the original instruction and then customizing the template based on the data in original instruction. The method can also include optimizing the customized template during the compile time.

摘要翻译： 提供了使用指令集模拟器（ISS）来模拟指令集体系结构（ISA）的方法。 所述方法的一个示例性实施例包括在运行时间期间获取第一解码指令，其中在运行时间之前的编译时间期间从目标应用程序中的原始指令对解码指令进行解码。 解码的指令可以指定被配置为实现原始指令的功能的模板。 该方法还优选地包括确定所获取的指令是否从原始指令修改，然后如果指令未被修改则执行指定的模板。 该方法还可以包括在编译期间通过选择与原始指令相对应的模板来解码原始指令，然后基于原始指令中的数据自定义模板。 该方法还可以包括在编译期间优化自定义模板。

公开(公告)号：US08166467B2

公开(公告)日：2012-04-24

申请号：US11651988

申请日：2007-01-11

申请人： Partha Biswas ,  Laura Pozzi ,  Nikil Dutt ,  Paolo Ienne

发明人： Partha Biswas ,  Laura Pozzi ,  Nikil Dutt ,  Paolo Ienne

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem.We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8× over pure software execution. Moreover, the number of required memory-access instructions is reduced by two thirds on average, suggesting corresponding benefits on energy consumption.

摘要翻译： 指令集扩展（ISE）可以有效地用于加速嵌入式处理器的性能。 ISE选择的关键和困难任务通常由设计人员手动执行。 用于ISE生成的几种自动方法显示出良好的功能，但是在处理存储器访问方面仍然受到限制，因此它们不能直接解决内存墙问题。 我们在这里介绍第一个可以自动识别状态保持应用程序特定功能单元（AFU）的ISE识别技术，从而能够消除高速缓存和主内存中大量的内存流量。 我们通过SimpleScalar模拟器获得的周期精确的结果表明，具有架构可见存储增益的识别AFU明显高于以前的技术，并且在纯软件执行上平均加速为2.8倍。 此外，所需的内存访问指令的数量平均减少三分之二，这表明了对能耗的相应益处。

公开(公告)号：US20120105099A1

公开(公告)日：2012-05-03

申请号：US13286136

申请日：2011-10-31

申请人： Kazuyuki Tanimura ,  Nikil Dutt

发明人： Kazuyuki Tanimura ,  Nikil Dutt

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： H03K19/003 ,  H03K19/00392 ,  H03K19/096

摘要： Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.

摘要翻译： 公开了用于DPA攻击电阻安全电路设计的均匀双轨逻辑。 根据一个实施例，HDRL电路包括主要小区和互补小区，其中所述互补小区是所述主小区的相同副本。 HDRL电路包括第一组输入和第二组输入，其中第二组输入是第一组输入的否定。 HDRL电路的差分功率在DPA攻击阻力的水平上。

公开(公告)号：US20070276646A1

公开(公告)日：2007-11-29

申请号：US10599593

申请日：2004-09-30

申请人： Nikil Dutt ,  Mohammad Reshadi

发明人： Nikil Dutt ,  Mohammad Reshadi

IPC分类号： G06F9/45

CPC分类号： G06F9/45504

摘要： Methods for simulating an instruction set architecture (ISA) with a instruction set simulator (ISS) are provided. One exemplary embodiment of the methods includes fetching a first decoded instruction during a run time, where the decoded instruction is decoded from an original instruction in a target application program during a compile time preceding the run time. The decoded instruction can designate a template configured to implement the functionality of the original instruction. The method also preferably includes determining whether the fetched instruction is modified from the original instruction and then executing the designated template if the instruction was not modified. The method can also include decoding the original instruction during the compile time by selecting a template corresponding to the original instruction and then customizing the template based on the data in original instruction. The method can also include optimizing the customized template during the compile time.

摘要翻译： 提供了使用指令集模拟器（ISS）来模拟指令集体系结构（ISA）的方法。 所述方法的一个示例性实施例包括在运行时间期间获取第一解码指令，其中在运行时间之前的编译时间期间从目标应用程序中的原始指令解码解码指令。 解码的指令可以指定被配置为实现原始指令的功能的模板。 该方法还优选地包括确定所获取的指令是否从原始指令修改，然后如果指令未被修改则执行指定的模板。 该方法还可以包括在编译期间通过选择与原始指令相对应的模板来解码原始指令，然后基于原始指令中的数据自定义模板。 该方法还可以包括在编译期间优化自定义模板。

公开(公告)号：US20070162900A1

公开(公告)日：2007-07-12

申请号：US11651988

申请日：2007-01-11

申请人： Partha Biswas ,  Laura Pozzi ,  Nikil Dutt ,  Paolo Ienne

发明人： Partha Biswas ,  Laura Pozzi ,  Nikil Dutt ,  Paolo Ienne

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8× over pure software execution. Moreover, the number of required memory-access instructions is reduced by two thirds on average, suggesting corresponding benefits on energy consumption.

摘要翻译： 指令集扩展（ISE）可以有效地用于加速嵌入式处理器的性能。 ISE选择的关键和困难任务通常由设计人员手动执行。 用于ISE生成的几种自动方法显示出良好的功能，但是在处理存储器访问方面仍然受到限制，因此它们不能直接解决内存墙问题。 我们在这里介绍第一个可以自动识别状态保持应用程序特定功能单元（AFU）的ISE识别技术，从而可以消除高速缓存和主内存中大量的内存流量。 我们通过SimpleScalar模拟器获得的循环准确结果表明，具有架构可见存储增益的识别AFU明显高于以前的技术，与纯软件执行相比，平均加速速度为2.8倍。 此外，所需的内存访问指令的数量平均减少三分之二，这表明了对能耗的相应益处。