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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10134756B2

    公开(公告)日：2018-11-20

    申请号：US15608076

    申请日：2017-05-30

    申请人： Sun Il Shim ,  Seung Wook Choi

    发明人： Sun Il Shim ,  Seung Wook Choi

    IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L23/522

    摘要： A semiconductor device includes a plurality of cell gate electrodes on a semiconductor substrate. End portions of the cell gate electrodes include stepped-pad regions that extend in a direction parallel to a surface of the semiconductor substrate. Vertical structures are on the semiconductor substrate and pass through the plurality of cell gate electrodes. The vertical structures respectively include a channel layer. Upper peripheral transistors are disposed on the semiconductor substrate. The upper peripheral transistors include an upper peripheral gate electrode at a level higher than a level of the plurality of cell gate electrodes, body patterns passing through the upper peripheral gate electrode and electrically connected to the pad regions, and gate dielectric layers between the upper peripheral gate electrode and the body patterns.

    Driving circuit for non destructive non volatile ferroelectric random access memory
    2.
    发明授权
    Driving circuit for non destructive non volatile ferroelectric random access memory 有权
    非破坏性非挥发性铁电随机存取存储器的驱动电路

    公开(公告)号：US06392921B1

    公开(公告)日：2002-05-21

    申请号：US09900184

    申请日：2001-07-09

    申请人： Yong Tae Kim ,  Chun Keun Kim ,  Seong Il Kim ,  Sun Il Shim

    发明人： Yong Tae Kim ,  Chun Keun Kim ,  Seong Il Kim ,  Sun Il Shim

    IPC分类号： G11C1100

    CPC分类号： G11C11/22

    摘要： The driving circuit for an NDRO-FRAM includes several NDRO-FRAM (Non Destructive Non Volatile Ferroelectric Random Access Memory) cells each having a drain, a bulk, a source and a gate and arranged as a matrix. A plurality of reading word lines are separately connected to each drain of the NDRO-FRAM cells arranged in columns, and a plurality of writing word lines are separately connected to each bulk of the NDRO-FRM cells arranged in columns. Several data level transmission circuits for transmitting a data level of the NDRO-FRAM cells are also included, which are connected to a plurality of data level transmission circuits. Accordingly, the present invention is capable of reading and writing of data on the NDRO-FRAM cells.

    摘要翻译： NDRO-FRAM的驱动电路包括几个NDRO-FRAM（非破坏性非易失性铁电随机存取存储器）单元，每个单元具有漏极，体积，源极和栅极并且被布置为矩阵。 多个读取字线分别连接到排列成列的NDRO-FRAM单元的每个漏极，并且多个写入字线分别连接到以列布置的NDRO-FRM单元的大部分。 还包括用于发送NDRO-FRAM单元的数据电平的几个数据电平传输电路，其连接到多个数据电平传输电路。 因此，本发明能够读取和写入NDRO-FRAM单元上的数据。