公开(公告)号：US06281067B1

公开(公告)日：2001-08-28

申请号：US09439932

申请日：1999-11-12

申请人： Sun-Chieh Chien ,  Hal Lee ,  Jhy-Jeng Liu ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Hal Lee ,  Jhy-Jeng Liu ,  Wei-Wu Liao

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/10873

摘要： A self-aligned process for forming a silicide layer over word lines in DRAM and a silicide layer over transistors in a logic device region. A substrate that includes a memory cell region and a logic circuit region is provided. A first transistor and a second transistor are formed over the substrate. The first transistor is formed in the logic circuit region and includes a first gate conductive layer and a first source/drain region. The second transistor is formed in the memory cell region and includes a second gate conductive layer and a second source/drain region. A blocking layer is formed over both the first transistor and the second transistor. A portion of the blocking layer is removed to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer. The remaining blocking layer still covers the second source/drain region. A metal silicide layer is formed over the first gate conductive layer, the first source/drain region and the second gate conductive layer.

摘要翻译： 用于在DRAM中的字线上形成硅化物层的自对准工艺以及在逻辑器件区域中的晶体管上的硅化物层。 提供了包括存储单元区域和逻辑电路区域的基板。 第一晶体管和第二晶体管形成在衬底上。 第一晶体管形成在逻辑电路区域中，并且包括第一栅极导电层和第一源极/漏极区域。 第二晶体管形成在存储单元区域中，并且包括第二栅极导电层和第二源极/漏极区域。 在第一晶体管和第二晶体管两端形成阻挡层。 去除阻挡层的一部分以暴露第一栅极导电层，第一源极/漏极区域和第二栅极导电层。 剩余的阻挡层仍然覆盖第二源极/漏极区域。 在第一栅极导电层，第一源极/漏极区域和第二栅极导电层上形成金属硅化物层。

公开(公告)号：US06406974B1

公开(公告)日：2002-06-18

申请号：US09535497

申请日：2000-03-24

申请人： Der-Yuan Wu ,  Jhy-Jeng Liu

发明人： Der-Yuan Wu ,  Jhy-Jeng Liu

IPC分类号： H01L21761

CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/0921

摘要： A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. Thus a triple N well is formed. A fourth ion implantation step is performed to form a cell well surrounded by the annular longitudinal deep N well. The cell well lies above the transversal deep N well. The second mask layer is removed.

摘要翻译： 描述了形成三重N阱的方法。 在基板上形成第一图案掩模层。 执行第一离子注入步骤以在衬底中形成环形纵向深N阱。 执行第二离子注入步骤以在衬底中形成环形纵向浅N阱。 环形纵向浅N井位于环形纵向深N井的上方。 第一个掩模层被去除。 在基板上形成第二图案化掩模层。 执行第三离子注入步骤以形成由环形纵向深N阱包围的横向深N阱。 横向深N井与环形纵深N井连接。 因此形成三重N阱。 执行第四离子注入步骤以形成由环形纵向深N阱围绕的阱。 细胞井位于横向深N井之上。 去除第二掩模层。