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公开(公告)号:US12032889B2
公开(公告)日:2024-07-09
申请号:US17190336
申请日:2021-03-02
申请人: Synopsys, Inc.
发明人: Jong Beom Park
IPC分类号: G06F30/36 , G06F18/23213 , G06F30/373 , G06F30/39 , G06N7/00 , G06N20/10 , G06F119/06 , G06N20/00
CPC分类号: G06F30/36 , G06F30/373 , G06F30/39 , G05B2219/45028 , G06F18/23213 , G06F2119/06 , G06N7/00 , G06N20/00 , G06N20/10
摘要: Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.
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公开(公告)号:US20210271994A1
公开(公告)日:2021-09-02
申请号:US17190336
申请日:2021-03-02
申请人: Synopsys, Inc.
发明人: Jong Beom Park
摘要: Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.
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