公开(公告)号：US12074198B2

公开(公告)日：2024-08-27

申请号：US17453300

申请日：2021-11-02

Applicant: Analog Power Conversion LLC

Inventor： Amaury Gendron-Hansen ,  Dumitru Gheorge Sdrulla ,  Leslie Louis Szepesi

IPC: H01L29/06 ,  G06F30/39 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G06F119/08 ,  H01L29/16

CPC classification number: H01L29/0696 ,  G06F30/39 ,  H01L29/0856 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7802 ,  G06F2119/08 ,  H01L29/1608

Abstract: A tub of a semiconductor device includes a cool zone with a first projected operating temperature and a hot zone with a second projected operating temperature greater than the first projected operating temperature. A design parameter has a first value in the cool zone and a second value different from the first value in the hot zone. The difference configures the tub to dissipate less heat in the hot zone during operation of the semiconductor device than would be dissipated if the first and second values were equal. The design parameter may be, for example, a tub width, a source structure width, a JFET region width, a channel length, a channel width, a length of a gate, a displacement of a center of the gate relative to a center of a JFET region, a dopant concentration, or a combination thereof.

公开(公告)号：US12020948B2

公开(公告)日：2024-06-25

申请号：US17377634

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Jui He ,  Chih-Teng Liao

IPC: H01L21/3213 ,  G03F1/70 ,  G06F30/39

CPC classification number: H01L21/32137 ,  G03F1/70 ,  G06F30/39 ,  H01L21/32139

Abstract: Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

公开(公告)号：US12013643B2

公开(公告)日：2024-06-18

申请号：US17883576

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Tsong-Hua Ou ,  Wen-Hao Chen

IPC: H05K3/00 ,  G03F1/70 ,  G03F7/20 ,  G06F30/39 ,  H01L21/3213 ,  H05K3/06

CPC classification number: G03F7/2022 ,  G03F1/70 ,  G06F30/39 ,  H01L21/3213 ,  H05K3/0082 ,  H05K3/06 ,  H05K3/0005 ,  H05K3/068 ,  H05K2201/09781 ,  H05K2203/0557 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

公开(公告)号：US11955425B2

公开(公告)日：2024-04-09

申请号：US18168043

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L23/522 ,  G06F30/39 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G06F30/39 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/5221 ,  H01L23/528

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

公开(公告)号：US11942469B2

公开(公告)日：2024-03-26

申请号：US17344411

申请日：2021-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-An Lai ,  Shih-Wei Peng ,  Te-Hsin Chiu ,  Jiann-Tyng Tzeng ,  Chung-Hsing Wang

IPC: H01L27/118 ,  G06F30/39 ,  H01L27/02

CPC classification number: H01L27/0207 ,  G06F30/39 ,  H01L27/11803

Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.

公开(公告)号：US20240090190A1

公开(公告)日：2024-03-14

申请号：US18519559

申请日：2023-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Jen CHEN ,  Wen-Hsi LEE ,  Ling-Sung WANG ,  I-Shan HUANG ,  Chan-yu HUNG

IPC: H10B10/00 ,  G06F30/39 ,  H01L23/528 ,  H01L27/088

CPC classification number: H10B10/12 ,  G06F30/39 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/785

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.

公开(公告)号：US20240037309A1

公开(公告)日：2024-02-01

申请号：US18345389

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Liu ,  Shang-Chih Hsieh ,  Jian-Sing Li ,  Wei-Hsiang Ma ,  Yi-Hsun Chen ,  Cheok-Kei Lei

IPC: G06F30/392 ,  G06F30/347 ,  G06F30/39 ,  H01L27/02

CPC classification number: G06F30/392 ,  G06F30/347 ,  G06F30/39 ,  H01L27/0207

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

公开(公告)号：US11842137B2

公开(公告)日：2023-12-12

申请号：US17406699

申请日：2021-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Shun Li Chen ,  Wei-Cheng Lin

IPC: G06F30/00 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/39 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/39 ,  G06F30/394 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

公开(公告)号：US11754617B2

公开(公告)日：2023-09-12

申请号：US17432864

申请日：2020-01-24

Applicant: TANAZAWA HAKKOSHA CO., LTD.

Inventor： Keiichiro Yamamoto ,  Kazuo Tani ,  Masaharu Yano

IPC: G01R31/28 ,  G06F30/39 ,  G01R1/073 ,  H05K3/12 ,  H05K3/34

CPC classification number: G01R31/281 ,  G01R1/07328 ,  G06F30/39 ,  H05K3/1225 ,  H05K3/34

Abstract: It is an object of the present invention to provide a printed circuit board capable of accurately detecting disconnections of circuit patterns with an automatic circuit pattern inspecting device even when positions of mounting lands are slightly deviated from normal positions due to manufacturing errors.
For solving this object, the printed circuit board of the present invention is provided with a first mounting land 4a and a second mounting land 4b, and a first circuit pattern 6a and a second circuit pattern 6b on a surface thereof, wherein a first electric checker land 10a and a second checker land 10b which are electrically connected with the first mounting land 4a and the second mounting land 4b are provided on a surface of a wiring board 2.

公开(公告)号：US11748541B2

公开(公告)日：2023-09-05

申请号：US17510315

申请日：2021-10-25

Applicant: efabless corporation

Inventor： Bertrand Irissou ,  John M. Hughes ,  Lucio Lanza ,  Mohamed K. Kassem ,  Michael S. Wishart ,  Rajeev Srivastava ,  Risto Bell ,  Robert Timothy Edwards ,  Sherif Eid ,  Greg P. Shaurette

IPC: G06F30/39 ,  G06F30/30 ,  G06F30/33 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06F30/3323 ,  H01L23/00 ,  G06F119/18

CPC classification number: G06F30/39 ,  G06F30/30 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  H01L23/573 ,  G06F2119/18

Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.