中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

3 records (took 0.013 seconds)

    Separation and minimum wire length constrained maze routing method and system
    1.
    发明授权
    Separation and minimum wire length constrained maze routing method and system 有权

    公开(公告)号：US10192019B2

    公开(公告)日：2019-01-29

    申请号：US14496420

    申请日：2014-09-25

    Applicant: Synopsys, Inc.

    Inventor： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

    IPC: G06F17/50

    Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.

    Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio
    2.
    发明授权
    Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio 有权
    考虑布线需求比设计和制造集成电路的系统和方法

    公开(公告)号：US08875081B2

    公开(公告)日：2014-10-28

    申请号：US13778071

    申请日：2013-02-26

    Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

    Inventor： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

    Abstract translation: 描述了一种用于设计和制造集成电路的方法。 该方法使用线段的统计模型来精确估计块内最小长度正交线段的预期长度。 根据这些估计，该方法精确地估计所需的水平和垂直路由资源之间的比例，称为“H / V需求比”。从H / V需求比率来看，块的高度和宽度的准确估计可以是 决心。 此后，可以快速且准确地执行放置和布线，从而允许块被快速且成本有效地设计和制造。 还描述了一种设计具有有效的金属-1资源利用的集成电路的方法。

Patent Agency Ranking