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公开(公告)号:US11983474B1
公开(公告)日:2024-05-14
申请号:US17561371
申请日:2021-12-23
申请人: Synopsys, Inc.
发明人: Parijat Biswas , Badri Gopalan , Enzhi Ni , Danish Jawed , Ying Chen , Jiang Chen
IPC分类号: G06F30/30 , G01R31/3183 , G06F30/323 , G06F30/3308
CPC分类号: G06F30/3308 , G01R31/31835 , G01R31/318357 , G06F30/323
摘要: A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified connections in a database, and using, by a processor, connections retrieved from the database to simulate and verify the coverage areas of the IC design.