公开(公告)号：US08832615B2

公开(公告)日：2014-09-09

申请号：US13891062

申请日：2013-05-09

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co. Ltd.

Inventor： Ming Han Hsieh ,  Chih-Neng Hsu ,  Ming-Hui Hsieh

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/78

Abstract: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.

Abstract translation: 一种用于检测低功率IC模拟中的信号行为异常的方法，包括接收IC的电路设计和功率规格，根据功率规格确定至少一个功率序列检验规则，模拟电路设计和功率规格 以获得转储文件，基于所述转储文件识别所述至少一个功率序列检查规则的至少一个异常，以及生成与所识别的所述至少一个功率序列检查规则的异常相关的信息。 该方法还包括通过在波​​形窗口中显示与异常相关联的不正常信号的波形以及电路设计的一部分和/或与该异常相关联的功率规范的一部分来设置调试器中的上下文以调试异常 在文本窗口中出现异常。

公开(公告)号：US08943452B2

公开(公告)日：2015-01-27

申请号：US13720737

申请日：2012-12-19

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Chih-Neng Hsu ,  I-Liang Lin ,  Wen-Chi Feng

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract translation: 一种计算机实现的方法，用于通过将功率规格格式表示的功率规格及其相应的电路设计集成在称为功率图的电源原理图中来调试IC设计的功率方面。 功率图是通过使用通过将原始电路设计层次重新分组到由电力规范定义的新层次来生成的电力数据库来创建的。 功率图包含功率单元符号（如隔离单元，电平转换器，电源开关）和信号网，并可显示电源域之间的关系。 电源图还可以在连接电源域的信号之间显示电源规格和电路设计之间的不匹配或错误。 此外，功率图可以与模拟结果一起使用。

公开(公告)号：US20130305207A1

公开(公告)日：2013-11-14

申请号：US13891062

申请日：2013-05-09

Applicant: SYNOPSYS, INC. ,  SYNOPSYS TAIWAN CO. LTD.

Inventor： Ming Han Hsieh ,  Chih-Neng Hsu ,  Ming-Hui Hsieh

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/78

Abstract: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.

Abstract translation: 一种用于检测低功率IC模拟中的信号行为异常的方法，包括接收IC的电路设计和功率规格，根据功率规格确定至少一个功率序列检验规则，模拟电路设计和功率规格 以获得转储文件，基于所述转储文件识别所述至少一个功率序列检查规则的至少一个异常，以及生成与所识别的所述至少一个功率序列检查规则的异常相关的信息。 该方法还包括通过在波​​形窗口中显示与异常相关联的不正常信号的波形以及电路设计的一部分和/或与该异常相关联的功率规范的一部分来设置调试器中的上下文以调试异常 在文本窗口中出现异常。

公开(公告)号：US20140013293A1

公开(公告)日：2014-01-09

申请号：US13718979

申请日：2012-12-18

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Chih-Neng Hsu ,  I-Liang Lin ,  Wen-Chi Feng

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set and display current operating mode of the IC design to enable the IC design to be debugged under different operating modes.

Abstract translation: 与IC设计相关联的功率信息使用功率图图形和分层显示，从而提供用于描述IC的各个功率域和功率域内的父子关系之间的功率分布的直观方式。 每个功率域与用于控制功率域的功率控制相关联。 每个电源域的电源控制状态显示在电源图上。 功率图可以包括用于设置和显示IC设计的当前操作模式的令牌，以使IC设计能够在不同的操作模式下进行调试。

公开(公告)号：US20130275933A1

公开(公告)日：2013-10-17

申请号：US13720737

申请日：2012-12-19

Applicant: SYNOPSYS TAIWAN CO., LTD.

Inventor： Chih-Neng Hsu ,  I-Liang Lin ,  Wen-Chi Feng

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract translation: 一种计算机实现的方法，用于通过将功率规格格式表示的功率规格及其相应的电路设计集成在称为功率图的电源原理图中来调试IC设计的功率方面。 功率图是通过使用通过将原始电路设计层次重新分组到由电力规范定义的新层次来生成的电力数据库来创建的。 功率图包含功率单元符号（如隔离单元，电平转换器，电源开关）和信号网，并可显示电源域之间的关系。 电源图还可以在连接电源域的信号之间显示电源规格和电路设计之间的不匹配或错误。 此外，功率图可以与模拟结果一起使用。