公开(公告)号：US11651133B2

公开(公告)日：2023-05-16

申请号：US17031547

申请日：2020-09-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Po-Sheng Wang ,  Chao Yuan Cheng ,  Chien-Chi Tien ,  Yangsyu Lin

IPC分类号： G06F30/392 ,  H01L27/02 ,  H01L27/118 ,  G06F119/18

CPC分类号： G06F30/392 ,  H01L27/0207 ,  H01L27/11807 ,  G06F2119/18 ,  H01L2027/11824 ,  H01L2027/11881

摘要： A method of forming an integrated circuit includes placing a first cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on the layout design. Placing the first cell layout design includes placing a first active region layout pattern adjacent to a first cell boundary, placing a second active region layout pattern adjacent to a second cell boundary, and placing a first set of active region layout patterns between the first and second active region layout patterns, according to a first set of guidelines. The first set of guidelines includes selecting transistors of a first type with a first driving strength and transistors of a second type with a second driving strength. In some embodiments, the first, second and first set of active region layout patterns extend in the first direction, and are on a first layout level.