公开(公告)号：US20230187283A1

公开(公告)日：2023-06-15

申请号：US18167442

申请日：2023-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/76232 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/823481

Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

公开(公告)号：US20210351086A1

公开(公告)日：2021-11-11

申请号：US17384888

申请日：2021-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.

公开(公告)号：US20200350214A1

公开(公告)日：2020-11-05

申请号：US16933088

申请日：2020-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.

公开(公告)号：US20190334035A1

公开(公告)日：2019-10-31

申请号：US15962181

申请日：2018-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Ta-Chun LIN ,  Rei-Jay HSIEH ,  Yung-Chih WANG ,  Wen-Huei GUO ,  Kuo-Hua PAN ,  Buo-Chin HSU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.

公开(公告)号：US20180308769A1

公开(公告)日：2018-10-25

申请号：US15635308

申请日：2017-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/76232 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.

公开(公告)号：US20220320086A1

公开(公告)日：2022-10-06

申请号：US17848875

申请日：2022-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Han WU ,  Chie-Iuan LIN ,  Kuei-Ming CHANG ,  Rei-Jay HSIEH

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first source/drain epitaxy structures and bottom of the second source/drain epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first source/drain epitaxy structures and the bottom the second source/drain epitaxy structures.

公开(公告)号：US20190122940A1

公开(公告)日：2019-04-25

申请号：US16221740

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.

公开(公告)号：US20180277536A1

公开(公告)日：2018-09-27

申请号：US15628728

申请日：2017-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Han WU ,  Chie-Iuan LIN ,  Kuei-Ming CHANG ,  Rei-Jay HSIEH

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.