公开(公告)号：US20230343404A1

公开(公告)日：2023-10-26

申请号：US18345530

申请日：2023-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Gu-Huan LI ,  Tung-Cheng CHANG ,  Perng-Fei YUH ,  Chia-En HUANG ,  Chun-Ying LEE LEE ,  Yih WANG

IPC分类号： G11C17/18 ,  G11C17/16 ,  H10B20/20

CPC分类号： G11C17/18 ,  G11C17/16 ,  H10B20/20

摘要： A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.