-
公开(公告)号：US20240312543A1
公开(公告)日：2024-09-19
申请号：US18672623
申请日：2024-05-23
发明人： Yih WANG , Hiroki NOGUCHI
IPC分类号： G11C17/12 , G11C11/4074 , G11C11/408 , G11C11/4094 , G11C17/16 , H01L21/8234
CPC分类号： G11C17/12 , G11C11/4074 , G11C11/4085 , G11C11/4094 , G11C17/16 , H01L21/823425
摘要： Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.
-
公开(公告)号：US20240071504A1
公开(公告)日：2024-02-29
申请号：US17898733
申请日：2022-08-30
发明人： Pei-Chun LIAO , Yu-Kai CHANG , Yi-Ching LIU , Yu-Ming LIN , Yih WANG , Chieh LEE
摘要： A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.
-
公开(公告)号：US20230343404A1
公开(公告)日：2023-10-26
申请号：US18345530
申请日：2023-06-30
发明人： Gu-Huan LI , Tung-Cheng CHANG , Perng-Fei YUH , Chia-En HUANG , Chun-Ying LEE LEE , Yih WANG
摘要： A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.
-
公开(公告)号：US20230050710A1
公开(公告)日：2023-02-16
申请号：US17401907
申请日：2021-08-13
发明人： Gu-Huan LI , Tung-Cheng CHANG , Perng-Fei YUH , Chia-En HUANG , Chun-Ying LEE , Yih WANG
IPC分类号： G11C17/18 , H01L27/112 , G11C17/16
摘要： A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.
-
公开(公告)号：US20230023505A1
公开(公告)日：2023-01-26
申请号：US17692996
申请日：2022-03-11
发明人： Chieh LEE , Chia-En HUANG , Yi-Ching LIU , Wen-Chang CHENG , Yih WANG
IPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C5/06
摘要： A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.
-
公开(公告)号：US20220028439A1
公开(公告)日：2022-01-27
申请号：US17154514
申请日：2021-01-21
发明人： Yi-Ching LIU , Chia-En HUANG , Yih WANG
摘要： A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, a first bit line, a second bit line and a first source line. The first bit lines extends in a first direction, and is coupled to the first memory cell, the second memory cell and the first select transistor. The second bit line extends in the first direction, and is coupled to the first select transistor. The first source line extends in the first direction, is coupled to the first memory cell and the second memory cell, and is separated from the first bit line in a second direction different from the first direction.
-
公开(公告)号：US20210376154A1
公开(公告)日：2021-12-02
申请号：US17185549
申请日：2021-02-25
发明人： Meng-Han LIN , Chia-En HUANG , Han-Jong CHIA , Martin LIU , Sai-Hooi YEONG , Yih WANG
IPC分类号： H01L29/78 , G11C11/22 , H01L27/1159 , H01L29/66
摘要： A ferroelectric field-effect transistor (FeFET) configured as a multi-bit storage device, the FeFET including: a semiconductor substrate that has a source region in the semiconductor substrate, and a drain region in the semiconductor substrate; a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack, the gate stack including a ferroelectric layer over the semiconductor substrate, and a gate region over the ferroelectric layer. The transistor also includes first and second ends of the ferroelectric layer which are proximal correspondingly to the source and drain regions. The ferroelectric layer includes dipoles. A first set of dipoles at the first end of the ferroelectric layer has a first polarization. A second set of dipoles at the second end of the ferroelectric layer has a second polarization, the second polarization being substantially opposite of the first polarization.
-
公开(公告)号：US20240331771A1
公开(公告)日：2024-10-03
申请号：US18741201
申请日：2024-06-12
发明人： Meng-Sheng Chang , Chia-En HUANG , Yi-Ching LIU , Yih WANG
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/003
摘要： Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.
-
公开(公告)号：US20240331760A1
公开(公告)日：2024-10-03
申请号：US18743950
申请日：2024-06-14
发明人： Chieh LEE , Chia-En HUANG , Yi-Ching LIU , Wen-Chang CHENG , Yih WANG
IPC分类号： G11C11/4091 , G11C5/06 , G11C11/4094 , G11C11/4096 , H03K19/20
CPC分类号： G11C11/4091 , G11C5/063 , G11C11/4094 , G11C11/4096 , H03K19/20
摘要： A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.
-
公开(公告)号：US20240185895A1
公开(公告)日：2024-06-06
申请号：US18439982
申请日：2024-02-13
摘要： A system includes a high bandwidth memory (HBM) arranged into portions including memory cells, the HBM further including a differentiated dynamic voltage and frequency scaling (DDVFS) device to perform the following: for a first set of one or more of the memory cells in a first one of the portions, the first set including a first one of the memory cells, controlling a temperature of the first set based on one or more first environmental signals corresponding to at least a first transistor in the first memory cell; and for a second set of one or more of the memory cells in a second one of the portions, the second set including a second one of memory cells, controlling a temperature of the second set based on one or more second environmental signals corresponding to at least a second transistor in the second memory cell.
-
-
-
-
-
-
-
-
-
搜索结果
43 条记录 (耗时 0.026 秒)
