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    Memory device
    2.
    发明授权
    Memory device 有权

    公开(公告)号：US11735238B2

    公开(公告)日：2023-08-22

    申请号：US17855107

    申请日：2022-06-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-An Lai ,  Chung-Cheng Chou ,  Yu-Der Chih

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C13/00 ,  G11C7/14

    CPC分类号： G11C7/222 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/14 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069

    摘要： A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

    MEMORY DEVICE CURRENT LIMITER
    5.
    发明申请
    MEMORY DEVICE CURRENT LIMITER 有权

    公开(公告)号：US20220366980A1

    公开(公告)日：2022-11-17

    申请号：US17816005

    申请日：2022-07-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chung-Cheng Chou ,  Tien-Yen Wang

    IPC分类号： G11C13/00

    摘要： A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

    Integration of magneto-resistive random access memory and capacitor
    9.
    发明授权
    Integration of magneto-resistive random access memory and capacitor 有权

    公开(公告)号：US10522591B2

    公开(公告)日：2019-12-31

    申请号：US14066978

    申请日：2013-10-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chung-Cheng Chou ,  Ya-Chen Kao ,  Tien-Wei Chiang

    IPC分类号： H01L27/22 ,  H01L43/12 ,  H01L43/10

    摘要： The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.