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公开(公告)号：US20240161822A1
公开(公告)日：2024-05-16
申请号：US18417325
申请日：2024-01-19
发明人： Wei-jer Hsieh , Yu-Hao Hsu , Zhi-Hao Chang , Cheng Hung Lee
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.
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公开(公告)号：US20230041094A1
公开(公告)日：2023-02-09
申请号：US17669673
申请日：2022-02-11
发明人： Tsung-Hsien Huang , Wei-jer Hsieh , Tsung-Yuan Huang , Yu-Hao Hsu
IPC分类号： G11C11/418
摘要： A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. The power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.
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公开(公告)号：US20220026475A1
公开(公告)日：2022-01-27
申请号：US16935608
申请日：2020-07-22
发明人： Chia-Chen Kuo , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： G01R19/165 , H02H1/00 , H02H9/02
摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
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公开(公告)号：US12125525B2
公开(公告)日：2024-10-22
申请号：US17669673
申请日：2022-02-11
发明人： Tsung-Hsien Huang , Wei-jer Hsieh , Tsung-Yuan Huang , Yu-Hao Hsu
IPC分类号： G11C11/418
CPC分类号： G11C11/418
摘要： A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. The power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.
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公开(公告)号：US12119040B2
公开(公告)日：2024-10-15
申请号：US17832186
申请日：2022-06-03
发明人： Zhi-Hao Chang , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： G11C11/4074 , G11C11/4072 , G11C11/4093
CPC分类号： G11C11/4074 , G11C11/4072 , G11C11/4093
摘要： A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.
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公开(公告)号：US11915746B2
公开(公告)日：2024-02-27
申请号：US17743073
申请日：2022-05-12
发明人： Wei-jer Hsieh , Yu-Hao Hsu , Zhi-Hao Chang , Cheng Hung Lee
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.
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公开(公告)号：US11913980B2
公开(公告)日：2024-02-27
申请号：US18178900
申请日：2023-03-06
发明人： Chia-Chen Kuo , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： H02H9/00 , G01R19/165 , H02H1/00 , H02H9/02
CPC分类号： G01R19/16519 , G01R19/16538 , H02H1/0007 , H02H9/02
摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
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公开(公告)号：US20230298657A1
公开(公告)日：2023-09-21
申请号：US17832186
申请日：2022-06-03
发明人： Zhi-Hao Chang , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： G11C11/4074 , G11C11/4093 , G11C11/4072
CPC分类号： G11C11/4074 , G11C11/4072 , G11C11/4093
摘要： A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.
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公开(公告)号：US11598794B2
公开(公告)日：2023-03-07
申请号：US16935608
申请日：2020-07-22
发明人： Chia-Chen Kuo , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： H02H9/00 , G01R19/165 , H02H1/00 , H02H9/02
摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
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公开(公告)号：US20220270674A1
公开(公告)日：2022-08-25
申请号：US17743073
申请日：2022-05-12
发明人： Wei-jer Hsieh , Yu-Hao Hsu , Zhi-Hao Chang , Cheng Hung Lee
IPC分类号： G11C11/419
摘要： A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.
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